基于FPGA的极化码译码研究及实现

发布时间：2018-06-16 18:53

本文选题：FPGA + 极化码　；参考：《电子技术应用》2017年06期

【摘要】：在二进制离散无记忆信道中极化码可以达到其信道极限容量,并且实现的复杂度较低,这在通信领域无疑是一个重大突破,因此在FPGA中实现极化码的译码有着非常重要的研究意义。首先介绍了SC(Successive Cancellation)译码算法,并将该算法的蝶形结构改进为线形结构从而提高了译码效率;接着对译码算法做了包括最小和译码、定点量化和资源共享的改进,以便于在硬件中更容易实现;最后在FPGA中实现了极化码的译码并给出了测试波形以及对不同编码块长度的综合资源进行了对比。实验结果表明,译码的最高频率可达145 MHz,吞吐率可达36.4 Mbps。
[Abstract]:In binary discrete memoryless channel, polarization code can reach its channel limit capacity, and the complexity of implementation is low, which is undoubtedly a great breakthrough in the field of communication. Therefore, the decoding of polarization codes in FPGA is of great significance. This paper first introduces the SC-Succtive decoding algorithm, and improves the butterfly structure of the algorithm into a linear structure, which improves the decoding efficiency, and then improves the decoding algorithm including minimum sum decoding, fixed-point quantization and resource sharing. Finally, the decoding of polarization code in FPGA is realized, and the test waveform is given, and the comprehensive resources of different coding block lengths are compared. The experimental results show that the maximum frequency of decoding is up to 145 MHz and the throughput is 36.4 Mbps.
【作者单位】：四川大学电子信息学院;
【分类号】：TN791;TN911.22

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