数字阵列雷达信号处理研究及实现

发布时间：2018-06-19 02:39

本文选题：数字阵列雷达 + 信号处理　；参考：《电子科技大学》2017年硕士论文

【摘要】：数字阵列雷达由于采用数字波束形成(DBF)直接控制雷达发射波束,对于复杂环境下弱小的目标检测和高速运动目标的跟踪有很大的优势。本文主要研究数字阵列雷达实验系统中信号处理部分,包括算法研究、FPGA实现和系统测试。基于A/D直采的软件化雷达有着很高的数据率,直接实时处理对于硬件来说是不可能实现的,因此采用多速率抽取技术将信号速率降低到合适的数据率。数字下变频(DDC)将高速率的中频信号混频到基带,然后利用多相滤波、积分梳状(CIC)滤波、半带(HB)滤波等多级滤波器处理后进行抽取。目前的雷达主要用大时宽大带宽的信号,这样兼顾距离分辨率和作用距离,大时宽大带宽信号经过脉冲压缩滤波器可以使回波宽脉冲变成窄脉冲,以达到提高距离分辨率的目的。再利用对消器和多普勒窄带滤波器组实现杂波抑制和运动目标检测,最后经过恒虚警(CFAR)处理检测出目标的距离和多普勒信息。所有信号处理环节先利用MATLAB进行设计仿真,然后利用采集数据进行验证,最后完成了FPGA模块的实现,得到实测和仿真结果相吻合。脉冲压缩是提高回波信号信噪比的方法,但是常用方法实现脉冲压缩的旁瓣很高,容易导致检测虚警。低旁瓣脉冲压缩方法一致是雷达信号处理的研究重点,所以本文在基带信号处理部分对时域和频域加窗抑制旁瓣进行了研究,又验证了利于工程实现的低旁瓣脉冲压缩方法,分别给出了各种方法得到的主瓣宽度和信噪比损失,最后还验证了基于RMMSE准则的自适应低旁瓣脉冲压缩的方法。通过测试FPGA实现结果和仿真结果的对比,验证了设计滤波器的合理性。在低旁瓣脉冲压缩滤波器设计中新方法结果低于-63dB。
[Abstract]:Digital array radar (DRA) has great advantages in detecting small and weak targets and tracking moving targets at high speed in complex environments because of the use of DBF (Digital Beamforming) to directly control the transmitting beams of radar. This paper mainly studies the signal processing in the digital array radar experimental system, including algorithm research, FPGA implementation and system testing. The software radar based on direct sampling of Ar / D has a high data rate, and direct real-time processing is impossible for hardware, so multi-rate decimation technology is used to reduce the signal rate to the appropriate data rate. Digital down conversion (DDC) mixes high rate intermediate frequency signals into the baseband, and then decimates by using multiphase filter, integrated comb CIC-filter, half-band HB-based filter and so on. At present, radar mainly uses the signal of large time and wide bandwidth, which takes into account the range resolution and the range of action. After pulse compression filter, the signal of large time and wide bandwidth can make the echo width pulse become a narrow pulse. In order to achieve the purpose of improving the range resolution. The clutter suppression and moving target detection are realized by using the canceller and Doppler narrowband filter bank. Finally, the range and Doppler information of the target are detected by CFAR (constant false alarm). All the signal processing links are designed and simulated by MATLAB, and then verified by the collected data. Finally, the FPGA module is implemented, and the measured results are consistent with the simulation results. Pulse compression is a method to improve signal-to-noise ratio (SNR) of echo signal, but the side lobe of pulse compression is very high, which can easily lead to false alarm detection. The low sidelobe pulse compression method is the focus of radar signal processing, so this paper studies the time domain and frequency domain windowed sidelobe suppression in the baseband signal processing part, and verifies the low sidelobe pulse compression method, which is easy to be realized in engineering. The main lobe width and SNR loss obtained by various methods are given respectively. Finally, the adaptive low sidelobe pulse compression method based on RMMSE criterion is verified. The rationality of the filter is verified by comparing the results of FPGA implementation and simulation. In the design of low sidelobe pulse compression filter, the result of the new method is lower than -63 dB.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN957.51

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