TD-LTE系统多用户下行共享信道实现关键技术研究

发布时间：2018-06-22 01:27

本文选题：TD-LTE + PDSCH　；参考：《电子科技大学》2016年硕士论文

【摘要】：无线技术的快速发展对硬件平台的性能有了越来越高的要求,为支持多种无线标准,TI推出了基于KeyStone I架构的多核DSP TMS320C6670。除了四个频率高达1.2GHz的DSP处理芯片外,TMS320C6670还集成了多种硬件加速器,用于减轻DSP处理器的处理需求。本文研究了基于TMS320C6670多核DSP平台的TD-LTE下行链路典型物理信道的实现与测试。论文主要研究了TD-LTE下行链路中的两个信道,下行共享信道(Physical Downlink Shared Channel,PDSCH)与广播信道(Physical Broadcast Channel,PBCH)。论文分析和研究了PDSCH和PBCH的传输原理,对处理流程进行子模块划分,对关键模块进行算法选型;运用Matlab搭建了链路级浮点仿真平台,将发端输出数据与第三方提供的标准数据进行对比,验证了发端处理流程的正确性。论文在高斯信道下进行了链路的性能仿真,验证了算法方案的可行性,也为基于DSP的定点实现提供了性能参考。论文重点研究了基于TMS320C6670芯片的多用户PDSCH和PBCH的实现关键技术。论文研究了下行多用户数据的发送过程,包括基于位协处理器(Bit Coprocessor,BCP)的比特级数据处理、多天线处理及端口映射、基于傅里叶变换协处理器(Fast Fourier Transformation Coprocessor,FFTC)的快速傅里叶变换。为实现峰值速率下的下行PDSCH多天线数据接收,论文分析并设计了四核联合的数据流水线处理过程,包括基于FFTC的分符号傅里叶变换、数据提取和分离、基于最小二乘和线性内插的信道估计、基于最小二乘的信道均衡、软解调、解扰、基于BCP的解速率匹配、利用Turbo译码协处理器(Turbo-Decoder Coprocessor,TCP3D)的译码以及CRC校验。论文研究了PBCH的盲检过程。由于PBCH解析时,该子帧在40ms周期内的相对位置和天线端口数目未知,PBCH接收端需要多次盲检以获得接入系统所需的信息。因此,论文详细分析了盲检过程和复杂度,并进行了DSP的软件实现。论文分析验证了实现方案资源分配的可行性;通过逐模块的数据比对和性能测试验证了模块实现的有效性和正确性;为充分测试系统性能,论文将链路与Matlab浮点仿真链路进行了误比特率性能对比,验证链路定点实现的性能。论文设计了下行链路联调方案,结合FPGA、射频板完成了下行链路的收发联调测试,测试平台经信道模拟器完成了性能和稳定性测试。
[Abstract]:With the rapid development of wireless technology, the performance of hardware platform is becoming more and more important. In order to support various wireless standards, TI has introduced a multi-core DSP TMS320C6670 based on KeyStone I architecture. In addition to four DSP processing chips with a frequency of up to 1.2 GHz, TMS320C6670 also integrates a variety of hardware accelerators to reduce the processing requirements of DSP processors. This paper studies the realization and test of typical physical channel of TD-LTE downlink based on TMS320C6670 multi-core DSP platform. In this paper, two channels in TD-LTE downlink, physical Downlink shared Channel (PDSCH) and physical broadcast Channel (PBCH) are studied. This paper analyzes and studies the transmission principle of PDSCH and PBCH, divides the processing flow into sub-modules, selects the key modules, builds a link level floating-point simulation platform with Matlab. The correctness of the process is verified by comparing the output data with the standard data provided by the third party. In this paper, the performance simulation of the link in Gao Si channel is carried out, which verifies the feasibility of the algorithm and provides a performance reference for the fixed-point implementation based on Gao Si. This paper focuses on the implementation of multi-user PDSCH and PBCH based on TMS320C6670 chip. The transmission process of downlink multiuser data is studied in this paper, including bit Coprocessor (BCP) based bit-level data processing, multi-antenna processing and port mapping, and Fast Fourier transform (FFT) based on Fast Fourier Transformation processor (FFTC). In order to realize the downlink PDSCH multi-antenna data receiving at the peak rate, this paper analyzes and designs the data pipeline processing process of the four-core union, including the split-symbol Fourier transform based on FFTC, data extraction and separation. Channel estimation based on least squares and linear interpolation, channel equalization based on least squares, soft demodulation, descrambling, rate matching based on BCP, decoding and CRC checking by Turbo decoding coprocessor (Turbo-Decoder processor TCP3D). The blind detection process of PBCH is studied in this paper. Because the relative position of the sub-frame and the number of antenna ports in the 40ms cycle are unknown, the PBCH receiver needs multiple blind checks to obtain the information needed for the access system. Therefore, the paper analyzes the blind detection process and complexity in detail, and carries out the software implementation of DSP. The paper analyzes and verifies the feasibility of realizing the resource allocation of the scheme; validates the validity and correctness of the module by module data comparison and performance testing; in order to fully test the system performance, In this paper, the link is compared with Matlab floating-point simulation link to verify the performance of link fixed-point implementation. In this paper, the downlink joint scheme is designed. Combined with FPGA, the radio frequency board completes the downlink transceiver test, and the test platform completes the performance and stability test through the channel simulator.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN929.5

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