基于时间数字转换器的全数字锁相环设计

发布时间：2018-07-31 07:54

【摘要】：随着计算机技术、信号处理和通信技术的不断发展,数字集成电路对系统时钟的性能要求越来越高,锁相环是提供高性能时钟的关键电路技术,随着半导体制造工艺的进步和发展,模拟锁相环已难以适应现代数字集成电路的要求,与之相比,全数字锁相环(ADPLL)具有集成度高、可移植性高、抗干扰能力强、设计周期短、可编程性好等特点,成为国内外锁相环领域的研究热点。本文研究了基于时间数字转换器(TDC)的全数字锁相环的设计。该ADPLL采用基于TDC的结构,由TDC、数控振荡器、鉴频鉴相控制器构成,其中的TDC采用计数器型TDC和游标延时链TDC相结合的结构,以提高TDC的分辨率。整个电路采用全定制和半定制相结合的设计方法,首先建立了 ADPLL的行为级模型,并通过仿真验证了 ADPLL的功能;在此基础上进行ADPLL的系统设计和电路设计,并通过数模混合仿真验证了 ADPLL的前仿真性能;最后完成了 ADPLL的版图设计和后仿真。本文的ADPLL最高能够提供1.5GHz的时钟,电路采用0.18μm CMOS工艺设计,包含焊盘在内的芯片面积为0.8mm2,后仿真结果显示其频率捕获范围为605MHz～2.03GHz,锁定时间小于3μs,在输出信号频率为1.5GHz时,周期抖动的峰峰值小于22ps,周期间抖动的RMS值小于5ps,在1.8V的电源电压下,电路总功耗约为20mW,满足设计指标要求。在数字集成电路不断发展的趋势下,本文设计的全数字锁相环对于锁相环的研究具有一定意义,对信号处理和通信系统的实现具有实际应用价值。
[Abstract]:With the development of computer technology, signal processing and communication technology, the performance of digital integrated circuit (DIC) is becoming more and more high. PLL is the key circuit technology to provide high performance clock. With the progress and development of semiconductor manufacturing technology, analog PLL has been difficult to adapt to the requirements of modern digital integrated circuits. Compared with the full digital PLL (ADPLL), it has high integration, high portability, strong anti-interference ability and short design period. Due to its good programmability, it has become a research hotspot in the field of PLL at home and abroad. This paper studies the design of all-digital phase-locked loop based on time-digital converter (TDC). The structure of the ADPLL is based on TDC, which is composed of TDC, numerical controlled oscillator and frequency phase discriminator. The TDC adopts the structure of counter TDC and Vernier delay chain TDC to improve the resolution of TDC. The whole circuit is designed by the combination of full customization and semi customization. Firstly, the behavior level model of ADPLL is established, and the function of ADPLL is verified by simulation, and then the system design and circuit design of ADPLL are carried out. The pre-simulation performance of ADPLL is verified by digital-analog hybrid simulation. Finally, the layout design and post-simulation of ADPLL are completed. The ADPLL in this paper can provide the clock of 1.5GHz up to the maximum. The circuit is designed in 0.18 渭 m CMOS process. The chip area including welding pad is 0.8mm2.After the simulation results show that the frequency capture range is 605mHz 2.03GHz, the locking time is less than 3 渭 s, and when the output signal frequency is 1.5GHz, The peak value of the periodic jitter is less than 22 pss. the RMS value of the jitter during the cycle is less than 5 ps. the total power consumption of the circuit is about 20 MW at 1.8 V power supply voltage, which meets the design requirements. With the development of digital integrated circuits, the all-digital phase-locked loop designed in this paper has a certain significance for the research of phase-locked loop, and has practical application value for the realization of signal processing and communication system.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.8

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