宽带数字接收机前端系统研究与设计
发布时间：2018-08-05 10:44
【摘要】：射频前端系统作为接收机最重要的一部分,一直是无线接收机研究的重点,也是接收机实现较困难的部分之一。随着数字处理技术的快速发展,数字电路在通信系统中比重越来越大。但是A/D转换器直接量化采样高频信号还具有相当的难度,因此普遍利用前端系统将高频信号下变频到中频再进行中频数字化的方案。射频前端系统如何有效的接收有用信号,抑制无用信号对有用信号的干扰,一直是一个重要的研究课题。本论文拟设计适用于30-1200MHz宽带数字接收机的前端系统电路,与普通通信接收机前端系统不同,本论文采用宽带扫描式超外差接收机前端电路的设计路线。它的典型特征是具有一个宽带捷变频的本振和一个宽带或可跟踪的预选器。该前端系统采用两次变频的方案,引入了两级混频电路。为了实现宽带数字接收机的扫描与分析功能,采取可变中频的方案,即采用70MHz高中频实现宽带扫描功能,采用21.4MHz低中频实现窄带分析功能。为了实现接收机的高分辨率,本方案采用宽带大步进本振源1与窄带小步进本振源2组合控制的方案,并且利用串行接口完成快速配置,同时提供了控制芯片的关键代码。本论文的撰写工作按照实际课题先论证后设计的方法,主要设计工作包括以下三个部分:(1)利用二次变频的超外差模型设计前端整体链路。结合工程实践分析了设计思路,将系统指标做分解。利用工程中实用的估算公式预算并验证前端系统指标需求。利用ADS软件搭建前端电路链路等效模型,插入AC仿真控制器与增益控制模块预算链路各功能模块的增益状态,搭建频率合成器链路模型预算了一本振等效电路的相位噪声。(2)利用插入损耗法设计了一个截止频率为1250MHz的椭圆函数微带低通滤波器,用于滤除输入信号的镜像频率和本振的反向辐射。采用阶梯阻抗微带滤波器模型,通过计算查询椭圆函数归一化表逆向算出微带滤波器各枝节电长度,再通过AppCAD工具计算出物理尺寸,最后利用HFSS软件建模仿真出S11、S21和VSWR曲线,得到插损、带外抑制和驻波比等关键指标,再通过优化处理得到了最优的设计参数。(3)采用混频环模型和DDS内插锁相环模型设计了两个频率合成器。本振源1利用Analog Device公司的ADF4151鉴相器和HITTITE公司的HMC440QS16G鉴相器设计了一个混频环方案,实现了输出频率1560MHz-2730MHz步进10MHz的双环电路。本振源2利用ADF4002鉴相器和AD9915直接数字频率合成器设计了一个DDS内插环方案,实现了输出频率1450MHz-1518.6MHz步进为1KHz的单环电路。在设计过程中将理论计算与工程实践融合,详细叙述了频率合成器的设计原理与方法。其次利用ADIsimPLL、ADIsimDDS软件仿真出频域和时域的各项指标,最后在Altium Designer画图软件设计原理图和PCB图纸,并给出最终的测试结果。
[Abstract]:As the most important part of the receiver, the RF front end system is always the focus of the wireless receiver, and is also one of the difficult parts of the receiver. With the rapid development of the digital processing technology, the proportion of digital circuits in the communication system is becoming more and more serious. But it is quite difficult to quantify the high frequency signal directly by the A/D converter. So it is an important research topic how the RF front end system receives the useful signal effectively and restraining the interference from the useful signal. This paper is designed to be used in the front of the 30-1200MHz wideband digital receiver. The end system circuit is different from the common communication receiver front-end system. This paper uses a broadband scanning ultra heterodyne receiver front-end circuit. Its typical feature is a broadband frequency agile local oscillator and a broadband or traceable preselector. The front end system uses two frequency conversion schemes and introduces two stage mixing power. In order to realize the scanning and analysis function of the wideband digital receiver, the scheme adopts the variable medium frequency scheme, that is, adopting the 70MHz high school frequency to realize the wideband scan function and using the 21.4MHz low IF frequency to realize the narrow band analysis function. In order to realize the high resolution of the receiver, this scheme uses the broadband and large step source 1 and the narrow band small step of the local oscillator source. In this paper, the main design work includes the following three parts: (1) design the whole link of the front end using the superheterodyne model of two frequency conversion. The design idea is analyzed and the system index is decomposed. The practical estimation formula in the project is used to budget and verify the index requirements of the front end system. The ADS software is used to build the equivalent model of the front-end circuit link, insert the AC simulation controller and the gain control module, and build the link model budget of the frequency synthesizer. Phase noise of an equivalent circuit. (2) an elliptic function microstrip low pass filter with cut-off frequency of 1250MHz is designed by insertion loss method, which is used to filter the image frequency of the input signal and the reverse radiation of the local oscillator. The step impedance microstrip filter model is used to reverse the micrograph of the calculated query ellipse function. With the power saving length of each branch of the filter, the physical size is calculated by AppCAD tool. Finally, S11, S21 and VSWR curves are simulated by HFSS software. The key parameters such as insertion loss, off band suppression and Bobbi are obtained, and the optimal design parameters are obtained by optimization. (3) the mixing loop model and DDS interpolated phase locked loop model are designed. Two frequency synthesizers. The source 1 uses Analog Device's ADF4151 phase detector and HITTITE's HMC440QS16G phase detector to design a mixing ring scheme, which realizes the double loop circuit of the output frequency 1560MHz-2730MHz step 10MHz. This oscillator 2 designs a DDS within a ADF4002 phase discriminator and a AD9915 direct digital frequency synthesizer. In the design process, the theoretical calculation and engineering practice are fused and the design principle and method of frequency synthesizer are described in detail. Secondly, the parameters of frequency domain and time domain are simulated by using ADIsimPLL and ADIsimDDS software, and finally in Altium Designer drawing. The software design schematic diagram and PCB drawings are given, and the final test results are given.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN858
[Abstract]:As the most important part of the receiver, the RF front end system is always the focus of the wireless receiver, and is also one of the difficult parts of the receiver. With the rapid development of the digital processing technology, the proportion of digital circuits in the communication system is becoming more and more serious. But it is quite difficult to quantify the high frequency signal directly by the A/D converter. So it is an important research topic how the RF front end system receives the useful signal effectively and restraining the interference from the useful signal. This paper is designed to be used in the front of the 30-1200MHz wideband digital receiver. The end system circuit is different from the common communication receiver front-end system. This paper uses a broadband scanning ultra heterodyne receiver front-end circuit. Its typical feature is a broadband frequency agile local oscillator and a broadband or traceable preselector. The front end system uses two frequency conversion schemes and introduces two stage mixing power. In order to realize the scanning and analysis function of the wideband digital receiver, the scheme adopts the variable medium frequency scheme, that is, adopting the 70MHz high school frequency to realize the wideband scan function and using the 21.4MHz low IF frequency to realize the narrow band analysis function. In order to realize the high resolution of the receiver, this scheme uses the broadband and large step source 1 and the narrow band small step of the local oscillator source. In this paper, the main design work includes the following three parts: (1) design the whole link of the front end using the superheterodyne model of two frequency conversion. The design idea is analyzed and the system index is decomposed. The practical estimation formula in the project is used to budget and verify the index requirements of the front end system. The ADS software is used to build the equivalent model of the front-end circuit link, insert the AC simulation controller and the gain control module, and build the link model budget of the frequency synthesizer. Phase noise of an equivalent circuit. (2) an elliptic function microstrip low pass filter with cut-off frequency of 1250MHz is designed by insertion loss method, which is used to filter the image frequency of the input signal and the reverse radiation of the local oscillator. The step impedance microstrip filter model is used to reverse the micrograph of the calculated query ellipse function. With the power saving length of each branch of the filter, the physical size is calculated by AppCAD tool. Finally, S11, S21 and VSWR curves are simulated by HFSS software. The key parameters such as insertion loss, off band suppression and Bobbi are obtained, and the optimal design parameters are obtained by optimization. (3) the mixing loop model and DDS interpolated phase locked loop model are designed. Two frequency synthesizers. The source 1 uses Analog Device's ADF4151 phase detector and HITTITE's HMC440QS16G phase detector to design a mixing ring scheme, which realizes the double loop circuit of the output frequency 1560MHz-2730MHz step 10MHz. This oscillator 2 designs a DDS within a ADF4002 phase discriminator and a AD9915 direct digital frequency synthesizer. In the design process, the theoretical calculation and engineering practice are fused and the design principle and method of frequency synthesizer are described in detail. Secondly, the parameters of frequency domain and time domain are simulated by using ADIsimPLL and ADIsimDDS software, and finally in Altium Designer drawing. The software design schematic diagram and PCB drawings are given, and the final test results are given.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN858
【参考文献】
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