通信信号侦察接收机与FMCW雷达信号处理机的研究与实现

发布时间：2018-08-20 18:23

【摘要】：在现代战争中,电子战可以说是一种特殊的作战形式,也是一种至关重要的作战手段。在电子战中,所有对抗及进攻形式都需要以电子侦察作为基础。本论文第一部分介绍的通信信号侦察接收机就是应用于电子侦查领域的一种技术手段,它针对的是通信信号。随着战场电磁环境的日益复杂,对通信信号侦察接收机的要求越来越多,论文中的接收机采用信道化数字接收机的结构,能更好的满足多信号同时处理、全概率截获的要求。论文首先分析了一般意义上的数字接收机,然后给出了基于多相滤波结构的信道化数字接收机,进一步引入快速傅里叶变换(FFT)的概念,得出了信道化数字接收机的高效结构。同时,论文针对“同一个信号出现在相邻信道中会无法识别”这一问题,采用了基于瞬时测频方法的信道判决准则。本文在理论框架的基础上,完成了在现场可编辑逻辑门阵列(FPGA)平台上的硬件实现过程。由于多相滤波结构的特殊要求,论文设计了并行的FFT运算处理单元,并且作了优化,以达到尽可能节省资源的目的。本文对信道化数字接收机的理论设计和FPGA算法设计,都进行了仿真,验证了设计的正确性。通信信号侦察接收机属于一种被动的探测体制,而本文第二部分介绍的FMCW雷达则属于主动探测雷达。随着我国经济突飞猛进的发展,汽车保有量快速增长,与此同时,交通安全问题也日益严重。本文第二部分讲的调频连续波(FMCW)雷达信号处理机,就是应用于交通安全领域的智能化信息采集设备。FMCW雷达,是以调频连续波信号为发射信号来获得目标信息的雷达体制,具有无距离模糊、较高的测距测速精度、重量轻、体积小、低概率截获等优点。本文依托实验室承接的雷达信号处理的省重点科研项目,主要介绍了FMCW雷达的相关原理及FPGA算法设计过程。在这一部分,首先介绍了FMCW雷达如何获取目标的距离、速度、方位角等信息,并讨论了距离—速度耦合现象出现的原因及如何解决这一问题。由于FMCW雷达信号处理机主要针对的是运动目标,因此论文还介绍了如何去掉固定目标干扰以及解决多目标显示的问题。论文仅介绍了项目的部分内容,主要是FMCW雷达信号处理机在FPGA中的算法设计。在本文的FPGA算法设计部分,详细的介绍了两维FFT运算、对消运算的数据处理过程,包括各模块中数据的存储结构。
[Abstract]:In modern warfare, electronic warfare can be said to be a special form of warfare, but also a vital means of warfare. In electronic warfare, all forms of confrontation and attack need to be based on electronic reconnaissance. The communication signal reconnaissance receiver introduced in the first part of this thesis is a kind of technical means applied in the field of electronic investigation, which is aimed at the communication signal. With the increasing complexity of battlefield electromagnetic environment, more and more communication signal reconnaissance receiver is required. The receiver in this paper adopts the structure of channelized digital receiver, which can better meet the requirements of multi-signal simultaneous processing and full probability interception. In this paper, the general digital receiver is analyzed, then the channelized digital receiver based on polyphase filter is presented. The concept of fast Fourier transform (FFT) is further introduced, and the efficient structure of channelized digital receiver is obtained. At the same time, aiming at the problem that the same signal can not be recognized in the adjacent channel, a channel decision criterion based on instantaneous frequency measurement method is adopted. Based on the theoretical framework, this paper completes the hardware implementation process on the field editable logic gate array (FPGA) platform. Due to the special requirement of polyphase filter structure, parallel FFT processing unit is designed and optimized to save resources as much as possible. The theoretical design of channelized digital receiver and the design of FPGA algorithm are simulated in this paper to verify the correctness of the design. The communication signal reconnaissance receiver belongs to a passive detection system, while the FMCW radar described in the second part of this paper belongs to the active detection radar. With the rapid development of economy in our country, the number of cars is increasing rapidly, meanwhile, the traffic safety problem is becoming more and more serious. In the second part of this paper, the signal processor of FM CW (FMCW) radar, which is used in traffic safety field, is an intelligent information acquisition equipment. FMCW radar is a radar system which uses FM CW signal as transmitting signal to obtain target information. It has the advantages of no range ambiguity, high ranging accuracy, light weight, small volume, low probability interception and so on. This paper mainly introduces the principle of FMCW radar and the design process of FPGA algorithm based on the scientific research project of radar signal processing. In this part, we first introduce how FMCW radar can obtain the range, velocity and azimuth of the target, and discuss the reason of the range-velocity coupling phenomenon and how to solve this problem. Because the FMCW radar signal processor is mainly aimed at moving targets, this paper also introduces how to remove the fixed target interference and solve the problem of multi-target display. This paper only introduces part of the project, mainly the algorithm design of FMCW radar signal processor in FPGA. In the part of FPGA algorithm design in this paper, the data processing process of two-dimensional FFT operation and cancellation operation is introduced in detail, including the data storage structure of each module.
【学位授予单位】：烟台大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN957.51;TN97

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