TPC译码算法研究及FPGA实现
发布时间：2018-08-23 14:45
【摘要】：通信系统中,通常使用信道编码来提高系统性能。Turbo乘积码(TPC)是一种结构简单而且具有良好的误码率性能和完整的理论推导的编码方法。在实际中得到广泛的应用。现在已经有高性能的编译码芯片产品被广泛的应用于通信、信息存储等方面。但是由于技术的封锁,国内无法获得高性能的Turbo编译码芯片。编译码芯片在工程中需要主控芯片的驱动,并为其分配相应的布线空间和I/O资源。因此以合理的算法为基础,通过FPGA实现编译码系统可以节省资源,实现高速并行处理,而且具有良好的可移植性。本文从TPC的基本理论出发,分别对传统的理论进行分析,通过研究译码参数对译码输出的影响。对现有的译码算法从逻辑设计的角度进行调整,主要目的是设计出译码速度高、性能稳定以及资源占用小的编译码系统。并对TPC的主流译码算法进行以下研究:硬判决算法可以运用于特殊的单比特传输系统,并且高信噪比条件下具有良好性能。在FPGA工程实现中,结构简单、译码延时小、资源占用低等特点。在保留以上优点的基础上,采用错误图样调整并且迭代的方法提高误码率性能。本文通过Matlab仿真验证算法性能,以及FPGA逻辑时序图来进一步对算法进行实现以及结果验证。在软判决良好的误码率性能的基础上,研究译码过程中影响译码速度和性能的参数。并通过Matlab进行仿真验证。在尽可能不影响误码率性能的情况下,分别从数学计算、译码结构、译码参数以及译码流程上做出一定的调整。最终通过FPGA逻辑优化实现高吞吐率、低资源占用有良好的可移植性的编译码系统设计。
[Abstract]:In communication systems, channel coding is usually used to improve system performance. Turbo product code (TPC) is a simple coding method with good BER performance and complete theoretical derivation. It is widely used in practice. Nowadays, high performance codec chips have been widely used in communication, information storage and so on. However, due to the blockage of technology, high performance Turbo codec chips can not be obtained in China. Code and decode chips need to be driven by the main control chip in the engineering, and the corresponding wiring space and I / O resources are assigned to them. Therefore, based on the reasonable algorithm, the system can save resources and achieve high speed parallel processing through FPGA, and it has good portability. Based on the basic theory of TPC, this paper analyzes the traditional theory, and studies the effect of decoding parameters on decoding output. The main purpose of adjusting the existing decoding algorithms from the point of view of logic design is to design a codec system with high decoding speed, stable performance and low resource consumption. The main decoding algorithms of TPC are studied as follows: the hard decision algorithm can be applied to special single-bit transmission systems and has good performance under the condition of high signal-to-noise ratio (SNR). In the implementation of FPGA, the structure is simple, the decoding delay is small and the resource is low. On the basis of preserving the above advantages, error pattern adjustment and iterative method are used to improve the bit error rate (BER) performance. In this paper, the performance of the algorithm is verified by Matlab simulation, as well as the FPGA logic sequence diagram to further implement the algorithm and verify the results. On the basis of soft decision with good BER performance, the parameters affecting decoding speed and performance in decoding process are studied. The simulation results are verified by Matlab. Under the condition that the BER performance is not affected as much as possible, some adjustments are made from mathematical calculation, decoding structure, decoding parameters and decoding flow. Finally, the design of code and decode system with high throughput and good portability is realized by FPGA logic optimization.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22;TN791
本文编号：2199385
[Abstract]:In communication systems, channel coding is usually used to improve system performance. Turbo product code (TPC) is a simple coding method with good BER performance and complete theoretical derivation. It is widely used in practice. Nowadays, high performance codec chips have been widely used in communication, information storage and so on. However, due to the blockage of technology, high performance Turbo codec chips can not be obtained in China. Code and decode chips need to be driven by the main control chip in the engineering, and the corresponding wiring space and I / O resources are assigned to them. Therefore, based on the reasonable algorithm, the system can save resources and achieve high speed parallel processing through FPGA, and it has good portability. Based on the basic theory of TPC, this paper analyzes the traditional theory, and studies the effect of decoding parameters on decoding output. The main purpose of adjusting the existing decoding algorithms from the point of view of logic design is to design a codec system with high decoding speed, stable performance and low resource consumption. The main decoding algorithms of TPC are studied as follows: the hard decision algorithm can be applied to special single-bit transmission systems and has good performance under the condition of high signal-to-noise ratio (SNR). In the implementation of FPGA, the structure is simple, the decoding delay is small and the resource is low. On the basis of preserving the above advantages, error pattern adjustment and iterative method are used to improve the bit error rate (BER) performance. In this paper, the performance of the algorithm is verified by Matlab simulation, as well as the FPGA logic sequence diagram to further implement the algorithm and verify the results. On the basis of soft decision with good BER performance, the parameters affecting decoding speed and performance in decoding process are studied. The simulation results are verified by Matlab. Under the condition that the BER performance is not affected as much as possible, some adjustments are made from mathematical calculation, decoding structure, decoding parameters and decoding flow. Finally, the design of code and decode system with high throughput and good portability is realized by FPGA logic optimization.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.22;TN791
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