基于USB3.0接口的高速数据传输系统设计
发布时间：2018-10-26 07:34
【摘要】：针对目前存储测试系统中存有的数据传输慢,经常出现错误的显著问题,设计基于USB 3.0接口的高速数据传输系统。该设计以FPGA作为主控芯片,采用负延迟与乒乓缓存的方式将A/D转换的数据高速缓存到DDR2 SDRAM中。设计了GPIFⅡ通用可编程接口和手动DMA通道,实现了USB 3.0同步从FIFO模式的高速数据传输。系统分析测试和实验结果表明,该系统实现了数据的高速可靠传输,能有效解决大容量数据采集后的数据高速传输问题。
[Abstract]:A high-speed data transmission system based on USB 3.0 interface is designed in view of the obvious problems of slow data transmission and frequent errors in the current storage and testing system. In this design, FPGA is used as the main control chip, and negative delay and ping-pong buffers are used to cache the A- / D converted data into the DDR2 SDRAM. The GPIF 鈪，
本文编号：2295017
[Abstract]:A high-speed data transmission system based on USB 3.0 interface is designed in view of the obvious problems of slow data transmission and frequent errors in the current storage and testing system. In this design, FPGA is used as the main control chip, and negative delay and ping-pong buffers are used to cache the A- / D converted data into the DDR2 SDRAM. The GPIF 鈪，
本文编号：2295017
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