基于H.265编码的视频处理系统设计
发布时间：2018-11-13 08:56
【摘要】：随着视频技术在各个领域的深入应用,视频也向着更高的分辨率、更高的帧频、更高压缩率的方向发展。如果依旧采用H.264/AVC(Advanced Video Coding)的编码方式,由于其固定的宏块划分、基于上下文的熵编码和去块滤波的串行处理方式,使得在编码高清、超高清视频质量和编码效率上显得不足。新一代编码技术H.265/HEVC(High Efficiency Video Coding)应运而生。H.265/HEVC采用更大宏块、更为灵活的划块机制、更为精确的预测等一系列技术有效的提高了编码压缩性能。但是其复杂度是H.264/AVC的5倍至10倍,这意味着在压缩相同图像下,H.265/HEVC需要较H.264/AVC几倍的数据处理能力。这样就对处理器的处理性能及功耗等提出了挑战。同时带来的好处是:在提供同样的视频质量下,H.265/HEVC可以将数据带宽减少50%。这使得在不改变现有网络带宽的条件下传输更高分辨率和帧速率的高清和超高清视频成为了一种可能。本文是基于H.265/HEVC编码对高清、超高清视频进行处理。根据H.265/HEVC编码的复杂度,设计了一套基于DSP、高性能FPGA、大容量数据缓存模块和PCIe高速串行总线等的高带宽H.265/HEVC压缩编码的视频处理系统。该视频处理系统的核心编码器件是TI公司生产的TMS320C6678高性能DSP器件。其具有8个内核,主要实现H.265/HEVC编码算法。该视频处理系统的核心主控制器件是Xlinx公司生产的XC7K410T FPGA器件。完成编码处理器TMS320C6678与PC之间高速数据交换以及大容量和高带宽的原始视频序列和编码后数据流的缓冲。高速数据交换模块主要用于对原始视频序列的高速传输,采用高速串行接口现实,FPGA与PC之间的高速串行接口采用PCIe协议,其为新一代高速串行总线,具有传输速率快,传输稳定、可靠的特点;FPGA与DSP编码器之间高速串行接口采用SRIO协议,此协议是嵌入系统中芯片间、板级间高性能、低时延、少引脚、可靠的基于包交换的高速串行互连技术。视频缓存模块主要用于存取视频原始序列和压缩后的H.265码流,采用多块DDR3L颗粒并联实现缓存,DDR3L具有高带宽、大容量、低功耗的特点。最后,通过对本系统的各个接口模块进行仿真和调试,验证了该视频处理系统设计的物理逻辑可行性。利用TMS320C6678处理器实现了对YUV 4:2:0视频原始序列的H.265/HEVC标准编码。并通过PC端软件初步分析了H.265/HEVC压缩后的码流。实现表明该系统:基于H.265编码的由高性能DSP和高性能FPGA组成架构视频处理系统对于高清、超高清视频的压缩、传输、存储等是可行的。同时具有一定的研究价值和应用前景。
[Abstract]:With the further application of video technology in various fields, video is developing towards higher resolution, higher frame rate and higher compression ratio. If H.264/AVC (Advanced Video Coding) coding method is still adopted, because of its fixed macroblock partition, context-based entropy coding and de-blocking filtering serial processing, it makes high-definition coding. UHD video quality and coding efficiency is insufficient. A new generation of coding technology, H.265/HEVC (High Efficiency Video Coding), emerges as the times require. A series of techniques, such as larger macroblock, more flexible block mechanism and more accurate prediction, are used in H.265/HEVC to effectively improve the performance of coding compression. But its complexity is 5 to 10 times that of H.264/AVC, which means that H.265/HEVC needs several times as much data processing power as H.264/AVC in the same image compression. In this way, the processing performance and power consumption of the processor are challenged. At the same time, the benefits are that H.265/HEVC can reduce data bandwidth by 50% with the same video quality. This makes it possible to transmit high-definition and ultra-high-definition video with higher resolution and frame rate without changing the current network bandwidth. This paper is based on H.265/HEVC coding for high-definition, ultra-high-definition video processing. According to the complexity of H.265/HEVC coding, a high bandwidth H.265/HEVC compression coding system based on DSP, high performance FPGA, large capacity data buffer module and PCIe high speed serial bus is designed. The core encoder of this video processing system is TMS320C6678 high performance DSP device produced by TI Company. It has 8 kernels and mainly implements H.265/HEVC coding algorithm. The core controller of the video processing system is the XC7K410T FPGA device produced by Xlinx Company. High speed data exchange between TMS320C6678 and PC as well as buffering of raw video sequences and encoded data streams with large capacity and high bandwidth are completed. The high-speed data exchange module is mainly used for the high-speed transmission of the original video sequence. The high-speed serial interface between FPGA and PC is based on the PCIe protocol, which is a new generation of high-speed serial bus with high transmission rate. Stable and reliable transmission; The high speed serial interface between FPGA and DSP encoder adopts SRIO protocol, which is a high speed serial interconnection technology based on packet switching. The video buffer module is mainly used to access the original video sequence and compressed H.265 bitstream. The DDR3L has the characteristics of high bandwidth, large capacity and low power consumption. Finally, the physical logic feasibility of the design of the video processing system is verified by the simulation and debugging of each interface module of the system. The H.265/HEVC standard encoding of YUV 4:2:0 video sequence is realized by using TMS320C6678 processor. The code stream after H.265/HEVC compression is analyzed by PC software. The implementation shows that the video processing system based on H.265 encoding is feasible for the compression, transmission and storage of high-definition, ultra-high-definition video, which is composed of high performance DSP and high performance FPGA. At the same time, it has certain research value and application prospect.
【学位授予单位】：成都理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN919.81
本文编号：2328621
[Abstract]:With the further application of video technology in various fields, video is developing towards higher resolution, higher frame rate and higher compression ratio. If H.264/AVC (Advanced Video Coding) coding method is still adopted, because of its fixed macroblock partition, context-based entropy coding and de-blocking filtering serial processing, it makes high-definition coding. UHD video quality and coding efficiency is insufficient. A new generation of coding technology, H.265/HEVC (High Efficiency Video Coding), emerges as the times require. A series of techniques, such as larger macroblock, more flexible block mechanism and more accurate prediction, are used in H.265/HEVC to effectively improve the performance of coding compression. But its complexity is 5 to 10 times that of H.264/AVC, which means that H.265/HEVC needs several times as much data processing power as H.264/AVC in the same image compression. In this way, the processing performance and power consumption of the processor are challenged. At the same time, the benefits are that H.265/HEVC can reduce data bandwidth by 50% with the same video quality. This makes it possible to transmit high-definition and ultra-high-definition video with higher resolution and frame rate without changing the current network bandwidth. This paper is based on H.265/HEVC coding for high-definition, ultra-high-definition video processing. According to the complexity of H.265/HEVC coding, a high bandwidth H.265/HEVC compression coding system based on DSP, high performance FPGA, large capacity data buffer module and PCIe high speed serial bus is designed. The core encoder of this video processing system is TMS320C6678 high performance DSP device produced by TI Company. It has 8 kernels and mainly implements H.265/HEVC coding algorithm. The core controller of the video processing system is the XC7K410T FPGA device produced by Xlinx Company. High speed data exchange between TMS320C6678 and PC as well as buffering of raw video sequences and encoded data streams with large capacity and high bandwidth are completed. The high-speed data exchange module is mainly used for the high-speed transmission of the original video sequence. The high-speed serial interface between FPGA and PC is based on the PCIe protocol, which is a new generation of high-speed serial bus with high transmission rate. Stable and reliable transmission; The high speed serial interface between FPGA and DSP encoder adopts SRIO protocol, which is a high speed serial interconnection technology based on packet switching. The video buffer module is mainly used to access the original video sequence and compressed H.265 bitstream. The DDR3L has the characteristics of high bandwidth, large capacity and low power consumption. Finally, the physical logic feasibility of the design of the video processing system is verified by the simulation and debugging of each interface module of the system. The H.265/HEVC standard encoding of YUV 4:2:0 video sequence is realized by using TMS320C6678 processor. The code stream after H.265/HEVC compression is analyzed by PC software. The implementation shows that the video processing system based on H.265 encoding is feasible for the compression, transmission and storage of high-definition, ultra-high-definition video, which is composed of high performance DSP and high performance FPGA. At the same time, it has certain research value and application prospect.
【学位授予单位】：成都理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN919.81
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