基于可重构的密码算法的设计与实现

发布时间：2019-03-11 10:17

【摘要】：随着信息科技的快速发展,信息安全越来越受到人们的关注,密码技术是保障信息安全的核心技术。可重构计算技术应用于密码处理系统,使同一硬件实现多种密码算法,既满足了密码算法处理对性能的要求,同时又具有较高的灵活性,提高了密码系统的安全性,在商业以及军事等领域具有广阔的应用空间。本文深入分析了分组密码算法AES、 DES和哈希算法SHA-3的处理结构特点及基本操作特征,结合可重构计算结构的设计特点与方法,设计了一种实现AES、 DES和SHA-3算法的可重构密码处理结构RCPA.该结构主要包括可重构处理单元PE、控制配置单元CCU、存储单元MU、输入输出缓冲单元IOBU以及互联单元ICU。本文研究了三种密码算法的基本运算单元,对具有相似的运算单元进行了研究分析,设计了可重构基本处理单元。可重构基本处理单元根据控制配置信息进行重构,灵活完成不同密码算法所需的运算功能。论文基于Verilog HDL硬件描述语言对该可重构密码处理结构进行了原型设计,详述了AES、 DES和SHA-3密码算法在可重构密码处理结构上的优化与映射过程。该设计原型在Cyclone IV系列FPGA器件上进行了板级验证,并在65nm CMOS工艺标准单元库下进行了逻辑综合。根据ASIC综合性能和在RCPA上的映射结果,给出了500MHz时钟频率下三种密码算法的执行性能。实验结果表明,本文设计的针对AES、 DES和SHA-3密码算法的可重构密码处理结构具有较高的处理性能。其密码处理速度与一些专用可重构密码结构相比性能提高了3.7～4.4倍：与其它一些ASIC实现的密码处理芯片相比,接近其80%的处理性能。结果说明本文研究的RCPA既能保证密码算法应用的灵活性,又能达到较高的处理性能。
[Abstract]:With the rapid development of information technology, people pay more and more attention to information security. Cryptography is the core technology to guarantee information security. The reconfigurable computing technology is applied to the cryptographic processing system, which enables the same hardware to implement a variety of cryptographic algorithms, not only satisfies the performance requirements of cryptographic algorithm processing, but also has high flexibility, and improves the security of the cryptosystem. It has a wide range of applications in commercial and military fields. In this paper, the processing structure and basic operation characteristics of block cipher algorithm AES, DES and hash algorithm SHA-3 are analyzed in depth. Combined with the design characteristics and methods of reconfigurable computing structure, a realization of AES, is designed. The Reconfigurable Cipher processing Architecture of DES and SHA-3 algorithms RCPA. The structure mainly includes reconfigurable processing unit PE, control configuration unit CCU, storage unit MU, input and output buffer unit IOBU and interconnection unit ICU. In this paper, the basic operation units of three cryptographic algorithms are studied, the similar operation units are studied and analyzed, and the reconfigurable basic processing units are designed. The reconfigurable basic processing unit reconstructs according to the control configuration information and flexibly accomplishes the operation functions required by different cryptographic algorithms. In this paper, the prototype of the reconfigurable cryptosystem is designed based on Verilog HDL hardware description language, and the optimization and mapping process of AES, DES and SHA-3 cryptographic algorithms in reconfigurable cryptosystem are described in detail. The prototype is verified at the board level on Cyclone IV series FPGA devices, and the logic synthesis is carried out under the 65nm CMOS process standard cell library. According to the comprehensive performance of ASIC and the mapping results on RCPA, the performance of three cryptographic algorithms at 500MHz clock frequency is given. The experimental results show that the reconfigurable cryptographic structure designed in this paper for AES, DES and SHA-3 cryptographic algorithms has high processing performance. Compared with some special reconfigurable cryptosystems, the performance of cryptographic processing is 3. 7-4. 4 times higher than that of some other ASIC-implemented cryptographic chips, which is close to 80% of its processing performance. The results show that the RCPA can not only guarantee the flexibility of cryptographic algorithm application, but also achieve high processing performance.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN918.1

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