无线通信中的高阶QAM实现技术研究

发布时间：2019-06-28 16:16

【摘要】：4G时代,人们对移动通信和便携式通信的关注度越来越高。随着通信业务范围的不断扩大,数据量几乎呈爆炸增长态势,面对日益紧张的频谱资源,传统调制方式已经难以满足当前通信需求。QAM调制因频谱利用率高、抗干扰能力强等优点而广泛应用于各种有线通信、无线通信场合。本文主要研究高阶QAM的实现技术,并以无线通信为背景,在64QAM业务模式下完成整个通信系统的软硬件仿真、设计、实现以及测试等任务。其中,基带部分在FGPA中以全数字方式实现,射频部分借助AD9361软件无线电平台实现,具体研究工作如下:首先,设计系统传输方案,并在Simulink环境下搭建仿真模型,验证方案的可行性。针对收发机中的各子模块,本文给出了详细的原理设计和仿真结果。然后,将仿真模型在FPGA中定点实现,并在确定量化精度后,按照模块化设计原则分别在ISE和Modelsim中进行代码编写与功能仿真。对设计中的一些关键模块本文采取了相关优化措施,比如时钟部分采用全局时钟管理技术,保证时钟的同源同相性;载波同步算法和盲均衡算法设计时,选择双模式切换算法,并使用高频时钟作为计算时钟,从而加快算法收敛速度,提高系统通信效率。最后,利用Xilinx公司的ML605开发板和ADI公司的AD9361板卡完成硬件调试与系统测试工作,这部分是设计的重点也是难点。本文通过在PC端编写上位机软件实现对AD9361硬件平台的灵活配置功能,并在调试期间,根据晶振校准系数、数据时钟延迟等实际硬件特性不断调整配置参数,优化系统性能;数据接口设计时本文选择了高速LVDS传输模式,有效降低了噪声信号干扰,利用FPGA内部的IDDR和ODDR原语可以完成差分信号的边沿转换和数据重组工作。硬件调试结束之后,分别在Cable信道和Wireless信道下,完成64QAM信号的系统测试任务。最终的测试结果表明,系统各模块的逻辑设计与功能完全正确,本文在FPGA上较好地完成了64QAM通信系统的设计与实现任务。
[Abstract]:In the 4G era, people's attention to mobile communication and portable communication is getting higher and higher. With the expansion of the business scope of communication, the data volume is almost explosive, and in the face of the increasing frequency of spectrum resources, the traditional modulation method has been difficult to meet the current communication requirement. The QAM modulation is widely applied to various wired communication and wireless communication occasions due to the advantages of high spectrum utilization rate, strong anti-interference capability and the like. In this paper, the realization technology of high-order QAM is mainly studied, and the hardware and software simulation, design, implementation and test of the whole communication system are carried out in the 64 QAM service mode with the background of wireless communication. The baseband part is implemented in full-digital manner in the FGPA, and the RF part is implemented by the AD9361 software radio platform. The specific research work is as follows: First, the system transmission scheme is designed, and the simulation model is set up in the Simulink environment, and the feasibility of the scheme is verified. For each sub-module in the transceiver, the detailed principle design and simulation results are given in this paper. Then, the simulation model is realized at a fixed point in the FPGA, and after the quantization precision is determined, the code writing and the function simulation are carried out in the ISE and the Modelsim according to the modular design principle, respectively. Some key modules in the design have adopted relevant optimization measures, such as the use of global clock management technology in the clock part, and guarantee the homophase of the clock; when the carrier synchronization algorithm and the blind equalization algorithm are designed, the dual-mode switching algorithm is selected, And the high-frequency clock is used as the calculation clock, so that the convergence speed of the algorithm is accelerated, and the communication efficiency of the system is improved. Finally, using the ML605 development board of Xilinx and the AD9361 board of Analog Devices to complete the hardware debugging and system testing, this part is the focus of the design. In this paper, the flexible configuration function of the AD9361 hardware platform is realized by writing the upper computer software at the PC end, and the configuration parameters are constantly adjusted according to the actual hardware characteristics such as the crystal oscillator calibration coefficient and the data clock delay during the debugging, and the system performance is optimized; In the design of the data interface, the high-speed LVDS transmission mode is selected, the interference of the noise signal is effectively reduced, and the edge conversion and the data recombination of the differential signal can be completed by using the IDDR and ODDR primitives inside the FPGA. After the end of the hardware debugging, the system test task of the 64QAM signal is completed under the Cable and Wireless channels, respectively. The final test results show that the logic design and function of each module of the system are completely correct, and the design and implementation tasks of the 64QAM communication system are well completed in the FPGA.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN92

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