星间通信低功耗软件定义无线电的研究和设计

发布时间：2024-04-14 16:28

　　传统大体型卫星的研发(Research and Development,R&D)往往需要成千上百个团队协同工作。开发周期通常很长而且成本也很高。小卫星的发展已成为一个热门的研究话题。世界各地许多国家和组织正在探索在近地轨道(Lower Earth Orbit,LEO)上的星群中部署一颗中型母卫星和数百个笔记本电脑大小的卫星,旨在开发更多应用,如情报侦查、战时通信恢复、合成孔径雷达等。在单一平台上只采用单一的编程语言和单一的开发工具的传统设计方法不能很好地满足大规模生产和短开发周期的要求。与可充电设备中的通信相比,小卫星通信系统在尺寸,重量和功率(Size,Weight,and Power,SWaP)以及硬件资源方面有更为苛刻的限制。此外,小卫星数量的急剧增加,较小的星间间距使得卫星的可用频谱更加拥挤。因此,解决这些问题就需要:(1)一种新的设计方法用来提高设计效率并能快速进行原型机验证,一个具有并行发收、动态调整速率和信号带宽并支持多种射频(Radio Frequency,RF)协议标准能力的平台。(2)改进的和优化的算法、简化的结构以及新的方案用来降低计算复杂度、硬件资源使用...

【文章页数】：193 页

【学位级别】：博士

【文章目录】：
ABSTRACT
摘要
List of Symbols
List of Abbreviations
Chapter 1 Introduction
    1.1 Background
    1.2 Research Motivations
    1.3 Related Works
        1.3.1 Research Topics on Small Satellites
        1.3.2 Applications of MBD Approach
        1.3.3 SDR Implementations
        1.3.4 FPGA Implementations
        1.3.5 Research on MARC
    1.4 Research Objectives
    1.5 Main Contributions
    1.6 Organization
Chapter 2 Model-Based Design Approach for SDRs in ISCs
    2.1 Preliminary
    2.2 Features of SDRs in ISCs
        2.2.1 Power Supply
        2.2.2 Frequency Allocation
        2.2.3 Coding Schemes and Rate
        2.2.4 Modulation Types
    2.3 Superiorities of MBD for SDRs
    2.4 Model-Based Design Flow for SDRs
        2.4.1 ISC SDR Model
        2.4.2 Automatic Code Generation
        2.4.3 Deployment of Customized IP Cores
        2.4.4 Simulation
        2.4.5 In-the-loop Testing and Verification
    2.5 SDR Challenges in Small Satellites Application
        2.5.1 Space Environment Challenges
        2.5.2 Software Challenges
        2.5.3 Hardware Challenges
    2.6 Summary
Chapter 3 Low Power SDR Design for Transmitter Prototype
    3.1 Overview of SDR Platform and Transmitter Prototype
        3.1.1 Inner Architecture of ADC/DAC
        3.1.2 Inner Architecture of FPGA
        3.1.3 SDR Structure of Transmitter Prototype
    3.2 MBD for Transmitter Baseband Processor
        3.2.1 LDPC Encoder
        3.2.2 OQPSK Modulator
        3.2.3 Pulse Shaping Filter
    3.3 Transmitter RF Front End
    3.4 Summary
Chapter 4 Low Power SDR Design for Receiver Prototype
    4.1 SDR Structure of Receiver Prototype
    4.2 MBD for Receiver Baseband Processor
        4.2.1 Automatic Gain Control
        4.2.2 Frequency Compensation
        4.2.3 Timing Recovery
        4.2.4 Frame Synchronization
        4.2.5 Soft-Output Demodulator
        4.2.6 LDPC Decoder
    4.3 Receiver RF Front End
    4.4 Summary
Chapter 5 Low Power Scheme and SDR Design for Small Satellites Cluster
    5.1 Typical Structures of Small Satellites Cluster
    5.2 Inter-Satellite Link Equation
    5.3 Relay Model and SDR Design for Small Satellites Cluster
        5.3.1 System Model and its Capacity Region
        5.3.2 Application of a Joint Network LDPC Code over MARC
        5.3.3 Joint Network LDPC Decoding
        5.3.4 SDR Design for the Relay Satellite
        5.3.5 SDR Design for the Mother Satellite
    5.4 Simulation Results
    5.5 Summary
Chapter 6 FPGA Implementation and Performance Analysis
    6.1 Interfaces Between the Host Computer and SDR Platform
        6.1.1 Bit Data Generation Module
        6.1.2 Data Packing and Unpacking Module
        6.1.3 Data Printing Module
        6.1.4 Transmitter and Receiver Configuration
    6.2 Real-Time Test
        6.2.1 Test Platform
        6.2.2 Signals Collection and Analysis
        6.2.3 Real-time Data Printing
        6.2.4 Signal Quality in Real-Time Transmission
    6.3 Hardware Utilization and Power Consumption
    6.4 Performance Analysis and Comparison
    6.5 Summary
Chapter 7 Conclusion
    7.1 Research Conclusion
    7.2 Limitations of Current Work
    7.3 Future Works
References
Acknowledgements
Resume



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