CMOS图像传感器测试平台的设计与实现

发布时间：2018-05-30 16:43

本文选题：CMOS测试平台 + FPGA　；参考：《大连理工大学》2016年硕士论文

【摘要】：CMOS图像传感器产业进入快速发展期,传感器的测试对于产品的研发生产至关重要,而国内可借鉴的完整的测试方案极少,国外主流的图像传感器测试机成本又极高。基于这种现状,本文设计了一款基于FPGA与USB3.0接口的CMOS图像传感器测试平台。平台承担了B1000和B4000两款CMOS传感器测试任务,且平台可扩展性强,并能以较小代价兼容更多未知类型CMOS图像传感器。系统硬件为插针拼接式结构,测试不同的传感器时更换不同的传感器图像采集电路与传输主板进行连接。传输主板以FPGA作主控,采用DDR2 SDRAM作为高速缓存,采用USB3.0芯片作为数据传输口。两个子板接口统一为B4000接口模式,B1000传感器的传感器驱动时序产生以及数据接收是在其传感器采集子板上进行,然后子板主控FPGA模拟B4000接口与主板进行通信。系统软件分三部分：高速传输主板FPGA程序,B1000子板FPGA程序和PC端程序。主板程序采用VHDL编写,涉及PC端指令的解析、高速LVDS数据接收和并行化、图像还原、位宽变换、DDR2 SDRAM驱动以及USB3.0芯片驱动；B1000子板采用Verilog HDL编写,涉及芯片驱动时序产生以及对B4000图像格式与控制总线的模拟；PC端程序采用C/C++编写,采用Cypress官方API实现底层通信,采用MFC类库进行界面开发。实现了图像数据的实时接收显示、传感器寄存器的读写、图像的导出和回放等功能。经测试,单独USB3.0芯片传输速率为318MB/s,单独DDR2 SDRAM传输速率为310MB/s,系统整体接口传输速率277MB/s,实现了传感器图像全帧全幅的实时传输。系统指令总线与数据总线信道均稳定无误码,实现了预定设计要求。本设计为CMOS图像传感器的测试提供了一种参考方案,有很强的应用价值。
[Abstract]:CMOS image sensor industry has entered a period of rapid development, sensor testing is very important for product development and production, but there are very few complete testing schemes available in China, and the cost of mainstream image sensor testing machines abroad is extremely high. Based on this situation, this paper designs a CMOS image sensor testing platform based on FPGA and USB3.0 interface. The platform takes on the task of testing B1000 and B4000 CMOS sensors, and the platform is extensible and can be compatible with more unknown CMOS image sensors at a lower cost. The hardware of the system is a pin splicing structure. When testing different sensors, different sensor image acquisition circuits are replaced to connect with the transmission motherboard. The main board uses FPGA as main control, DDR2 SDRAM as cache and USB3.0 chip as data transmission port. The two sub-board interfaces are unified into the B4000 interface mode and the sensor driver timing generation and data reception are carried out on the sensor acquisition sub-board, and then the sub-board master control FPGA simulates the B4000 interface to communicate with the main board. System software is divided into three parts: high-speed transmission motherboard FPGA program B 1000 sub-board FPGA program and PC program. The main board program is written with VHDL, which involves the analysis of PC side instructions, high-speed LVDS data receiving and parallelization, image restoration, bit width conversion DDR2 SDRAM driver and USB3.0 chip driver B1000 subboard written by Verilog HDL. The analog PC program of B4000 image format and control bus is written by C / C, Cypress official API is used to realize bottom communication, and MFC class library is used to develop interface. The functions of real-time receiving and displaying of image data, reading and writing of sensor register, export and playback of image are realized. The test results show that the transmission rate of single USB3.0 chip is 318MB / s, that of single DDR2 SDRAM is 310MB / s, and that of the whole system interface is 277MB / s. The system instruction bus and data bus channel are stable and correct code, and the predetermined design requirements are achieved. This design provides a reference scheme for the test of CMOS image sensor and has strong application value.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP212

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