基于FPGA的卷积神经网络加速器设计

发布时间：2018-06-07 08:18

本文选题：卷积神经网络 + 硬件加速　；参考：《电子科技大学》2017年硕士论文

【摘要】：随着计算机性能的不断发展,以及对机器学习领域的深入研究,卷积神经网络(convolutional neural network,CNN)成为了近年以来最为热门的机器学习算法之一。由于其复杂的网络结构和训练方法,卷积神经网络是极为耗费计算资源的一种算法。传统的卷积神经网络是基于通用中央处理器(central processing unit,CPU)执行计算的,这样的计算不但缓慢低效,而且难以满足实时性的计算要求。由于现场可编程门阵列(field-programmable gate array,FPGA)具有高度的并行性以及灵活性,能够更好的承担卷积神经网络的计算任务。本文基于FPGA硬件提出了对卷积神经网络计算的加速方法,使用该方法对ETL9B手写日本语数据库进行了识别验证,获得了99.7%的识别正确率,同时减少了约90%的时间消耗。首先,本文第一章简单介绍了卷积神经网络的基本概念以及应用背景。阐述了卷积神经网络算法的发展状况,尤其是基于硬件的卷积神经网络的现状及不足,提出了基于硬件卷积神经网络加速器设计方案。其次,在第二章中本文详细介绍了卷积神经网络的工作原理,包括图像卷积,池化采样,激活函数的计算以及反向传播的训练方法,文章还简要介绍了几种著名的卷积神经网络结构。再次,本文第三章详细阐述了基于坐标旋转数字计算方法(coordinate rotation digital computer,CORDIC)的激活函数计算原理,并且对传统的CORDIC算法进行了优化。提出了一种基于查找表和贪心策略相结合的综合旋转策略(unified rotation strategy,URS),加快了传统CORDIC算法的迭代收敛过程。第四章,详细分析了基于FPGA的卷积神经网络硬件加速器的设计,完成了CORDIC处理器的设计,卷积核的设计,池化采样模块的设计,以及控制模块的设计。最后,在第五章中给出了设计系统的仿真及测试结果,并且使用设计的系统对ETL9B手写日本语数据库进行了训练,验证了系统的可靠性。对比软件系统的训练结果,极大的缩减了训练时间,体现出FPGA在卷积神经网络训练中的优势。
[Abstract]:With the continuous development of computer performance and the in-depth study of machine learning, convolutional neural network has become one of the most popular machine learning algorithms in recent years. Because of its complex network structure and training method, convolution neural network is a very expensive algorithm. The traditional convolution neural network is based on the general central processor central processing unit CPU. This kind of computation is not only slow and inefficient, but also difficult to meet the requirements of real-time computing. Because field-programmable gate array (field-programmable gate array FPGA) has high parallelism and flexibility, it can take on the computing task of convolution neural network better. Based on FPGA hardware, an accelerated method for computing convolutional neural networks is proposed in this paper. The method is used to validate the recognition of ETL9B handwritten Japanese language database. The recognition accuracy is 99.7% and the time consumption is reduced by 90%. In the first chapter, the basic concept and application background of convolution neural network are introduced. This paper describes the development of convolution neural network algorithms, especially the current situation and shortcomings of hardware-based convolution neural networks, and puts forward the design scheme of the accelerator based on hardware convolution neural networks. Secondly, in the second chapter, the working principle of convolution neural network is introduced in detail, including image convolution, pool sampling, calculation of activation function and training method of back propagation. Several famous convolution neural networks are also briefly introduced in this paper. Thirdly, in chapter 3, the principle of coordinate rotation digital computer Cordic is discussed in detail, and the traditional CORDIC algorithm is optimized. An integrated rotation strategy based on lookup table and greedy strategy is proposed, which speeds up the iterative convergence of the traditional CORDIC algorithm. In chapter 4, the design of convolution neural network hardware accelerator based on FPGA is analyzed in detail. The design of CORDIC processor, convolution core, pool sampling module and control module are completed. Finally, the simulation and test results of the design system are given in Chapter 5, and the ETL9B handwritten Japanese language database is trained with the designed system to verify the reliability of the system. Compared with the training results of the software system, the training time is greatly reduced, which reflects the advantages of FPGA in the training of convolution neural networks.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791;TP183

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