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MEMS加速度传感器信号处理电路设计

发布时间:2018-10-24 22:34
【摘要】:MEMS(Microelectromechanical Systems)加速度传感器是MEMS器件中重要的一类,有着广泛的应用,如汽车的安全性和稳定性、生物医学应用、石油和天然气勘探以及电脑配件等。石油勘探最常用的方法之一就是地震勘探,在地震检测领域,与常规检波器相比,利用MEMS技术实现的检波器具有更好的线性度和动态范围,且具有更高的灵敏度等特点,成为目前发展主流。MEMS检波器主要包括电容加速度传感器和信号检测专用集成电路芯片(Application Specific Integrated Chip,ASIC)。MEMS传感器信号处理电路主要用来检测MEMS电容传感器敏感质量块所受到的加速度,并将其转换成电压信号。本文主要从MEMS电容加速度传感器电容检测原理出发,针对目前研究存在的加速度计线性度低等缺陷,结合CMOS工艺特点和已有的研究基础,提出了二阶模拟闭环力平衡反馈模式下开关电容电路检测方案。其读出电路主要包括电容补偿阵列、参考源、多相时钟、全差分开关电容电路、RC低通滤波和仪表放大器等。其中,全差分开关电容电路采用相关双采样技术消除失调,仪表放大器采用三运放结构,对差分信号进行单端输出,具有噪声小、精度高等特点。基于旺宏L50W 0.5μm工艺,针对该力平衡反馈模式对系统进行了时序设计,完成了读出电路设计分析与仿真验证、版图设计与后仿真验证及其流片。本文针对野外勘探ESD(Electrostatic Discharge)防护要求更为严苛,以及高压ESD防护高触发、低维持的难点,对读出电路进行全芯片ESD防护设计,芯片的I/O端口采用互补式的栅极耦合技术的PMOS和NMOS,电源端口采用栅极耦合技术的NMOS,有效提高了芯片的ESD防护等级。整体芯片前后仿验证均表明该系统具有线性度高、噪声和失调低等特点,并在旺宏L50W 0.5μm工艺下进行流片。
[Abstract]:MEMS (Microelectromechanical Systems) accelerometer is an important class of MEMS devices, which has a wide range of applications, such as car safety and stability, biomedical applications, oil and gas exploration and computer accessories. One of the most commonly used methods for petroleum exploration is seismic exploration. In the field of seismic detection, compared with the conventional geophone, the geophone realized by MEMS technology has better linearity and dynamic range, and has higher sensitivity and so on. MEMS geophone mainly includes capacitive acceleration sensor and signal detection chip (Application Specific Integrated Chip,ASIC). MEMS sensor signal processing circuit, which is mainly used to detect the acceleration of the sensitive mass block of MEMS capacitive sensor. And convert it into a voltage signal. Based on the principle of capacitance detection of MEMS capacitive accelerometer, this paper aims at the defects of low linearity of accelerometer, combining with the characteristics of CMOS process and the existing research foundation. In this paper, a second order analog closed loop force balance feedback detection scheme for switched capacitor circuits is proposed. The readout circuit includes capacitor compensation array, reference source, polyphase clock, fully differential switched capacitor circuit, RC low-pass filter and instrument amplifier. Among them, the fully differential switched capacitor circuit uses correlation double sampling technology to eliminate the misalignment, and the instrument amplifier adopts a three-stage operational amplifier structure, which outputs the differential signal with a single end, which has the characteristics of low noise and high precision. Based on Wanghong L50W 0.5 渭 m process, the timing design of the system is carried out for the force balance feedback mode. The readout circuit design analysis and simulation verification, layout design and post simulation verification and flow sheet are completed. Aiming at the more severe requirements of field exploration ESD (Electrostatic Discharge) protection, and the difficulties of high trigger and low maintenance of high voltage ESD protection, the whole chip ESD protection design of readout circuit is carried out in this paper. The I / O port of the chip adopts the complementary gate coupling technology PMOS and the NMOS, power port adopts the gate coupling technology NMOS, to effectively improve the ESD protection level of the chip. The simulation results show that the system has the characteristics of high linearity, low noise and misalignment, and the flow sheet is carried out in Wanghong L50W 0.5 渭 m process.
【学位授予单位】:湘潭大学
【学位级别】:硕士
【学位授予年份】:2017
【分类号】:TP212

【参考文献】

相关硕士学位论文 前3条

1 李乐乐;低功耗、高精度、宽共模输入范围仪表放大器的研究与设计[D];复旦大学;2013年

2 张文杰;MEMS加速度传感器读出电路设计[D];湘潭大学;2013年

3 林丽娟;基于20V NLDMOS结构的ESD防护器件的设计[D];电子科技大学;2012年



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