ATLAS液氩量能器触发读出系统Phase-I升级的光纤数据链路与控制链路设计

发布时间：2017-12-28 18:01

本文关键词：ATLAS液氩量能器触发读出系统Phase-I升级的光纤数据链路与控制链路设计　出处：《华中师范大学》2016年博士论文　论文类型：学位论文

【摘要】：ATLAS液氩量能器是ATLAS探测器的重要组成部分,用来测量LHC (Large Hadron Collider)对撞产生的高能粒子的能量。ATLAS合作组计划利用2018年LHC二期长停机期间对液氩量能器进行Phase-Ⅰ升级。为了能让ATLAS液氩量能器工作在LHC Run-3 (2018-2019年)期间3倍于当前亮度的环境下,液氩量能器Phase-Ⅰ升级的重点就是研发数字化触发系统,借此抑制背景噪声,以高效的从背景中筛选出有效事件。更高的探测能量、亮度和读出电子学更高的粒度都引起了数据传输量的显著扩增,因此光纤链路在ATLAS液氩量能器触发读出系统高速、海量数据的传输中起到了至关重要的作用。本文的主要研究工作是提出了光纤数据链路发送器芯片LOCx2中关键的编码方案,并在SoS 0.25μm CMOS工艺下实现了核心模块编码器,设计了低延时的链路后端数据接收器FPGA固件,且利用GBT-Link实现了对整个链路系统的有效监控。本文的具体研究内容和创新点主要表现在如下几个方面：1. ATLAS液氩量能器要求光纤数据链路的前端具备耐辐照能力、功耗≤100mW/Gbps、延迟≤75ns,整个数据链路的延迟≤150ns。目前业界仅有CERN开发的GBT-Link可工作于辐照环境,但其它指标均不满足要求。因此,SMU光电实验室为ATLAS合作组开发了一款符合要求的数据链路。该链路的前端包括数据发送器芯片LOCx2和激光驱动芯片LOCld2。它们都采用SoS 0.2μm CMOS工艺设计而成,该工艺使用蓝宝石作为绝缘衬底,对单事件闭锁免疫,具有天然的抗辐照特性。LOCx2中的编码器模块是数据链路前端低延迟、低编码开销、低功耗的关键模块。主要研究工作体现在以下三点：①提出了全新的"LOCic编码”,创造性的将12位的BCID (Bunch Cross Identification)信息编码到了4位字段之中,传输每帧112位的载荷数据相比于8B10B编码来说编码开销从33.9%降至了14.3%,大大降低了链路的功耗。该编码简洁的编码过程也易于实现低延迟的编码器。②编码器版图采用人工精确设计,且通过优化数字器件阈值电压和时钟树、使用流水线技术等方法将编码器的工作频率从该工艺库的极限100MHz提升至320MHz,进一步降低了延迟。③设计三时钟FIFO用以连接编码器与前端两ADC芯片,且使其容忍两个ADC芯片输出信号之间3.125ns的相位不定性。IOCx2芯片有两个数据发送通道,每个通道的输出速率为5.12Gbps,测试表明LOCx2的功耗仅为843mW,整个芯片的延迟≤27.2ns,其中IOCic编码器带来的延迟≤21ns,各指标达到ATLAS液氩量能器的需求。2.除了低延迟的编码器之外,为了降低整个数据链路的低延迟还需要设计低延迟的数据接收器。数据接收器由串并转换器和解码器构成,采用商用FPGA实现：①通过优化串行收发器IP核,使其能够接收5.12Gbps的高速串行数据,恢复出高速时钟,对数据进行采样并最终完成串并转换。②采用简洁的解码过程并且让解码器运行在尽量高的频率320MHz下,使延迟降到了最低。③根据单粒子翻转导致链路同步丢失时数据的特点,解码器实现了链路的快速再同步功能。光纤数据链路的测试表明,数据接收器可以成功实现链路的同步,恢复出原始数据和BCID信息,并通过CRC校验。链路的位差错率10-12,延迟≤74.25ns,远低于150ns。3.为了保证基于LOCx2芯片的光纤数据链路能够正常工作,本文采用GBT-Link实现了对应的控制系统,给光纤数据链路提供时钟、控制信号并监控系统的工作状态。控制链路在后端的FPGA上实现了GBT-Link协议、HDLC协议和通道命令协议收发器,以此完成与前端GBTx和GBT-SCA芯片的双向通讯,并最终利用GBTx和GBT-SCA芯片实现对系统的控制。测试表明在该控制链路的控制下,光纤数据链路能够稳定可靠的传输数据。
[Abstract]:The ATLAS liquid argon calorimeter is an important part of the ATLAS detector, which is used to measure the energy of the high energy particles produced by the collision of LHC (Large Hadron Collider). The ATLAS cooperation group plans to upgrade the Phase- I of the liquid argon calorimeter during the long shutdown period of the 2018 LHC two period. In order to make the ATLAS liquid argon calorimeter work in the environment of LHC Run-3 (2018-2019 years), which is 3 times the current brightness, the focus of Phase- I upgrade is to research and develop the digital trigger system, so as to suppress the background noise and effectively filter out effective parts from the background. Higher detection power, brightness and higher granularity of readout electronics have caused significant amplification of data transmission. Therefore, optical links play a crucial role in ATLAS liquid argon calorimeter trigger reading system's transmission of high-speed and massive data. The main work of this paper is to put forward the encoding scheme of fiber optic data link transmitter key chip LOCx2, and implement the core module in the SoS encoder 0.25 m CMOS technology, designed the back-end data link receiver FPGA firmware low time delay, and use GBT-Link to realize the effective monitoring of the link system. The main research contents and innovations are as follows: the front 1. ATLAS liquid argon calorimeter for fiber optic data link with radiation resistant ability, power consumption is less than or equal to 100mW/Gbps, the delay is less than or equal to 75ns, the data link delay is less than 150ns. At present, only CERN developed by the industry GBT-Link can work in the radiation environment, but other indicators do not meet the requirements. Therefore, the SMU optoelectronic laboratory has developed a data link that meets the requirements for the ATLAS cooperation group. The front end of the link consists of a data transmitter chip LOCx2 and a laser driver chip LOCld2. They are designed by SoS 0.2 m CMOS process. The sapphire insulation substrate has natural radiation resistance for single event latch up immunity. The encoder module in LOCx2 is the key module of low delay, low coding overhead and low power consumption in the front end of the data link. The main research work embodied in the following three points: 1. Put forward a new "LOCic encoding", creative 12 BCID (Bunch Cross Identification) encoding information to 4 bit field, transmission load data of each frame 112 compared to the 8B10B encoding for encoding overhead from 33.9% to 14.3%, greatly reduced link power. The coding succinct coding process is also easy to implement low latency encoders. Secondly, the encoder layout is manually designed accurately, and by optimizing the threshold voltage and clock tree of digital devices, and using pipelining technology, the working frequency of the encoder is increased from the limit 100MHz of the process library to 320MHz, further reducing the delay. The design of three clock FIFO is used to connect the encoder and the front end two ADC chip, and make it tolerate the phase uncertainty of the 3.125ns between the output signals of the two ADC chips. The IOCx2 chip has two data transmission channel, the output rate of each channel is 5.12Gbps. The tests show that the power consumption of LOCx2 is only 843mW, the delay is less than or equal to 27.2ns of the chip, the delay is less than or equal to 21ns the IOCic encoder brings, the index reached ATLAS liquid argon calorimeter demand. 2. in addition to low delay encoders, low latency data receivers are required in order to reduce the low latency of the entire data link. The data receiver is composed of serial to parallel converter and decoder. It is implemented by commercial FPGA. First, by optimizing the IP core of serial transceiver, it can receive high-speed serial data of 5.12Gbps, recover high-speed clock, sample data and complete serial to parallel conversion. (2) using a simple decoding process and allowing the decoder to run at a high frequency of 320MHz, the delay is reduced to a minimum. (3) the decoder realizes the fast re synchronization of the link, based on the characteristics of the data when the link is lost synchronously. The test of the fiber data link shows that the data receiver can achieve the synchronization of the link successfully, restore the original data and BCID information, and check it through the CRC. The link bit error rate 10-12, delay less than 74.25ns, far less than 150ns. 3., in order to ensure that the optical fiber data link based on LOCx2 chip can work normally, the corresponding control system is implemented by GBT-Link, which provides clock and control signals to the optical data link and monitors the working state of the system. The control link implements GBT-Link protocol, HDLC protocol and channel command protocol transceiver on the FPGA of the back end, so as to complete two-way communication with the front-end GBTx and GBT-SCA chips, and finally realize the control of the system by using GBTx and GBT-SCA chips. The test shows that the fiber data link can transmit data steadily and reliably under the control of the control link.
【学位授予单位】：华中师范大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：O572.214

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