ATLAS sTGC前端电子学测试关键技术研究

发布时间：2018-01-04 01:33

本文关键词：ATLAS sTGC前端电子学测试关键技术研究　出处：《中国科学技术大学》2017年博士论文　论文类型：学位论文

【摘要】：2012年,LHC上的ATLAS/CMS实验装置发现了 Higgs,标志着粒子物理基础科学进入了一个新的时代,LHC实验的下一步科学目标是精确测定Higgs粒子及其与物质场相互作用耦合,寻找超出标准模型以外的新粒子、新现象。为实现这一物理目标,LHC及其实验将于2018和2022年,分两阶段进行Phase 1和Phase 2升级,实验的探测器系统也将同步进行相应升级,以确保在高能高亮度质子对撞环境下有效采集数据和开展物理分析。本论文以研制ATLAS Phase 1 Muon谱仪端盖NSW sTGC新型探测器系统为需求,针对当前前端板高密度、大通道数量(升级需要1536块前端板,共322000通道),开展前端电子学测试技术研究,并设计了 256通道测试信号源和FEB配置测试板。本文首先分析sTGC探测器前端电子学测试需求和测试方法,通过对测试信号源研究,模拟前端探测器的输出信号,着力解决大规模、多通道探测器测试信号生成关键技术,为FEB提供不同工作模式的仿真信号来测试FEB的功能和性能,目前,可以提供六种模式的256路测试信号,同时,提供同步时钟信号和脉冲触发信号,能与FEB构成一个完整的测试系统。其次,针对新一代ASIC芯片测试和配置系统测试验证为需求,开发FEB配置测试板,研究以SCA为核心的配置芯片对FEB关键芯片的配置,主要包含对VMM3和TDS2的配置,实现了多种接口标准和通信协议的开发以及数据链路的验证等,为FEB原型板关键芯片配置和数据读出提供技术参考,并为最终的系统配置提供技术验证和支持。最后,以这两个板子为基础构建测试平台,该测试平台提供探测器测试信号仿真、前端电子学读出、系统配置来构建完整测试方案。对FEB进行了一系列测试,包括通道增益、阈值、基线测试等,其中测试信号源的注入测试能够替代探测器提供触发信号,进行FEB的功能验证。FEB配置测试板能够完成与SCA的数据通信,实现了对SCA芯片接口的操作与控制,包括E-link、SPI、I2C、GPIO等,并成功配置了 VMM3和TDS2,同时验证了 TDS2的4.8Gbps的高速数据传输功能。FEB配置测试板还在CERN进行了电子学集成测试,完成了与 Pad trigger和 Router 板的通信。论文的创新点主要有:1、多通道、高密度、可编程测试信号源研究,完成了测试方法和测试理论分析,实现多样式可控256路FEB板测试信号生成功能,提高了系统测试效率,构建测试平台并对其中的关键ASIC(VMM2)器件进行测试,并给出测试结果。2、针对FEB关键技术,设计FEB配置测试板,开发了多种数据接口协议,实现了利用GBT-SCA芯片对VMM3、TDS2的配置,同时验证了 4.8Gbps的TDS数据读出,测试结果表明现采用的技术能够满足将来FEB的实现需求。3、高速网络数据传输技术,研究并实现了基于FPGA的MAC层网络数据传输技术和计算机网卡直接网络编程方法,完成计算机与FPGA高速网络通信,传输速度测试可达926Mbps。
[Abstract]:In 2012, the discovery of Higgs by the ATLAS/CMS experimental device on the LHC marked the beginning of a new era in the basic science of particle physics. The next scientific goal of the LHC experiment is to accurately determine the Higgs particles and their interaction with the material field, and to find new particles and new phenomena beyond the standard model. LHC and its experiments will be upgraded to Phase 1 and Phase 2 in two phases in 2018 and 2022, and the detector system will be upgraded simultaneously. In order to ensure the effective data collection and physical analysis in the environment of high energy and high brightness proton collision, the NSW of the end cap of ATLAS Phase 1 Muon spectrometer is developed in this paper. New sTGC detector system is required. Aiming at the high density of front-end board and the number of large channels (1536 front-end boards are needed for upgrading, a total of 322000 channels are needed, the research on front-end electronics testing technology is carried out. And designed 256-channel test signal source and FEB configuration test board. Firstly, this paper analyzes the sTGC detector front-end electronic testing requirements and testing methods, through the research of the test signal source. The output signal of the front-end detector is simulated to solve the key technology of large-scale multi-channel detector test signal generation. The simulation signal of different working mode is provided for FEB to test the function and performance of FEB. At present, it can provide six modes of 256-channel test signal, at the same time, provide synchronous clock signal and pulse trigger signal, and can form a complete test system with FEB. Secondly. To meet the requirements of the new generation of ASIC chip test and configuration system test verification, the FEB configuration test board is developed, and the configuration of the key FEB chip based on SCA is studied. It mainly includes the configuration of VMM3 and TDS2, the development of various interface standards and communication protocols, and the verification of data links. It provides technical reference for the key chip configuration and data readout of FEB prototype board, and provides technical verification and support for the final system configuration. Finally, the test platform is built on the basis of these two boards. The test platform provides detector test signal simulation, front-end electronic readout, system configuration to build a complete test scheme. A series of tests on FEB, including channel gain, threshold, baseline test, etc. The injection test of test signal source can replace the detector to provide trigger signal, and the function verification of FEB. Feb configuration test board can complete the data communication with SCA. The operation and control of SCA chip interface are realized, including the E-link SPI I I 2C PIO, and the VMM3 and TDS2 are configured successfully. At the same time, it is verified that TDS2's 4.8Gbps high-speed data transmission function. Feb configuration test board is also tested in CERN. The communication with Pad trigger and Router board is completed. The main innovation of this paper is: 1: 1, multi-channel, high-density, programmable test signal source research. The test method and test theory analysis are completed, and the test signal generation function of multi-style controllable 256-channel FEB board is realized, and the system test efficiency is improved. Build the test platform and test the key ASIC VMM2 device, and give the test result. 2. According to the key technology of FEB, design the FEB configuration test board. A variety of data interface protocols are developed to realize the configuration of VMM3TDS2 using GBT-SCA chip. At the same time, the 4.8 Gbps TDS data readout is verified. The test results show that the current technology can meet the future FEB implementation requirements. 3, high-speed network data transmission technology. The MAC layer network data transmission technology based on FPGA and the direct network programming method of computer network card are studied and realized. The communication between computer and FPGA high-speed network is completed. The transmission speed test can reach 926 Mbps.
【学位授予单位】：中国科学技术大学
【学位级别】：博士
【学位授予年份】：2017
【分类号】：O572.2

【参考文献】