魂芯DSP软件流水框架的研究与实现

发布时间：2018-03-19 09:52

本文选题：多簇DSP　切入点：编译器优化　出处：《中国科学技术大学》2017年硕士论文　论文类型：学位论文

【摘要】：魂芯DSP(BWDSP)是一款采用分簇体系结构,支持超长指令字运行,通过在同一时钟周期发射多条指令的数字信号处理器。分簇结构的设计提高了指令的并行性,同时保证体系结构上不会有太高的硬件代价。本文以中电38所自主研制的魂芯DSP(BWDSP)编译系统中的后端软件流水优化为研究课题。本文的主要工作有以下几点:(1)本文首先论述了自主研发的魂芯DSP的主体框架结构,即其硬件架构和指令系统。同时介绍了 BWDSP平台上的Open64编译器,从Open64编译器的整体编译框架角度,详细描述编译器支持的中间语言结构以及后端中间代码表示。(2)软件流水优化技术是编译器后端一项重要的优化技术,对于具有循环的程序提高性能有着重要意义。软件流水的主要思想是挖掘循环迭代之间不同指令的并行性。通过对指令的重叠执行,充分利用平台中的硬件资源,提高程序的运行效率。本文的主要工作是在BWDSP平台上实现软件流水优化技术,采用经典的软件流水实现方法模调度框架。通过对模调度框架的分析,实现了模调度框架在BWDSP分簇结构上的移植。在实现模调度软件流水移植于BWDSP平台的基础上,本文还提出了一种激进的软件流水调度框架,改变了以往具有依赖环及归约变量的循环体无法进行软件流水的现状,实现了该种循环体在BWDSP平台的软件流水。通过典型的算法核心测试,实验证明,该框架能够使更多类型的循环实现软件流水。(3)在基于软件流水,循环展开,SIMD等优化思想的指导下,同时结合BWDSP体系结构中的指令特点,利用高效访存指令、能够提升循环执行效率的零开销循环机制、指令重排技术,结合具体功能函数的循环特性,本文对字符串与内存处理函数的指令级并行性进行挖掘。实验结果表明,这些库函数优化后的时间周期能够达到硬件平台限制下的理论运行时间1.5倍左右,对BWDSP平台整体性能提升具有重要意义。
[Abstract]:Soul Core DSP (BWDSP) is a kind of digital signal processor which adopts cluster architecture and supports very long instruction word running. The design of cluster structure improves the parallelism of instruction by transmitting more than one instruction in the same clock cycle. At the same time, it is guaranteed that the hardware cost will not be too high. This paper focuses on the optimization of the back-end software income in the Soulcore DSPO BWDSP-based compilation system developed by CLP 38. The main work of this paper is as follows: 1. First of all, the main frame structure of the self-developed soul core DSP is discussed. At the same time, it introduces the Open64 compiler on the BWDSP platform, from the angle of the whole compiling framework of the Open64 compiler, Describes in detail the intermediate language structure supported by the compiler and the back-end intermediate code representation. Income optimization technology is an important optimization technique for the compiler back-end. The main idea of software income is to exploit the parallelism of different instructions between iterations of the loop. By the overlapping execution of instructions, the hardware resources in the platform can be fully utilized. The main work of this paper is to realize the optimization technology of software income on the BWDSP platform, and to implement the method model scheduling framework by adopting the classical software income. This paper has realized the transplantation of module scheduling framework on BWDSP cluster structure. On the basis of realizing the migration of module scheduling software income to BWDSP platform, this paper also proposes a radical scheduling framework of software income. This paper changes the situation that the loop with dependent ring and reduced variables can not carry out software income in the past, and realizes the software income of this kind of loop on BWDSP platform. Through the typical algorithm core test, the experiment proves that the loop can not be used in software income. This framework can make more kinds of cycles realize software income. 3) under the guidance of optimized ideas such as the software income, the loop unfolded SIMD and so on, at the same time, combining the instruction characteristics in the BWDSP architecture, using the high efficiency memory access instruction. In this paper, we mine the parallelism between string and memory processing function at instruction level, which can improve the efficiency of loop execution, such as zero-overhead loop mechanism, instruction rearrangement technology, and the loop characteristic of specific function. The optimized time period of these library functions can reach about 1.5 times of the theoretical running time limited by hardware platform, which is of great significance to the overall performance improvement of BWDSP platform.
【学位授予单位】：中国科学技术大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332;TP311.5

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