有源延时单元与延时锁定环路
发布时间:2018-05-27 11:18
本文选题:延时电路 + 延时锁定环 ; 参考:《东南大学》2017年硕士论文
【摘要】:随着高速混合信号电路的发展,信号的时序对整体系统日渐产生着至关重要的影响。因此,设计电路时常需要添加若干延时单元,用于产生或补偿路径间的延时差异,以实现特定的性能要求。延时电路应用广泛,除了可以补偿不同信号链路间的延时差,还可以运用于宽带波束形成系统电路、有限冲激响应(FIR)滤波器、无限冲激响应(IIR)滤波器以及均衡器电路的设计中。因此,研究和设计高性能的延时电路具有重要的价值和意义。本文采用IBM 0.13μm SiGe BiCMOS工艺设计了有源延时电路和延时锁定环路。本文在介绍延时电路基本原理和比较各种延时电路结构的基础上采用了 gm-C结构的有源延时电路,并使用高性能的SiGeHBT管作为输入管,提高了延时电路的工作频带范围。延时电路通过调节可变电容改变延时时间,并利用电感峰化和射极负反馈技术拓展电路带宽。为了减少信号在输入输出端口的反射,设计的匹配电路可以保证延时电路在工作频带内反射系数小于-10dB。本文中的延时锁定环路可以调节延时电路的延时时间,使其在不同工艺角、温度和电压下的延时时间不变。延时锁定环路由延时电路、乘法器和V/I转换器电路组成。延时锁定环路具有负反馈调节功能,可以保证环路中的延时电路总延时为四分之一的时钟周期。为了减少了环路中各模块引入的相位误差,设计了全对称的四象限乘法器和低失调V/I转换器,可以有效提高延时锁定环路的锁定精度。设计完成的芯片尺寸为500μm×800μm,测试结果显示,在4-12GHz的工作频率范围内,单级延时电路的平均延时时间可以保持在8ps左右,当控制电压变化时,单级延时电路的延时时间可以从7.3ps变化到8.4ps。在延时电路的输入输出端加入的匹配电路,可以保证电路的S11和S22反射系数在0.2-25GHz内小于-10dB。当改变时钟信号频率时,延时锁定环路产生的控制电压可以调节延时电路的延时时间,并提高延时电路延时的稳定性。本文延时单元与延时锁定环路的设计,对今后低延时宽频带延时电路的设计和应用具有一定的意义。
[Abstract]:With the development of high speed mixed signal circuit, the timing of the signal is becoming more and more important to the whole system. Therefore, it is often necessary to add a number of delay elements to the circuit to generate or compensate for delay differences between paths in order to achieve specific performance requirements. Delay circuits are widely used in the design of wideband beamforming system circuits, finite impulse response (FIR) filters, infinite impulse response (IIR) filters and equalizer circuits in addition to compensating for delay differences between different signal links. Therefore, the research and design of high performance delay circuit has important value and significance. In this paper, the active delay circuit and delay locking loop are designed using IBM 0.13 渭 m SiGe BiCMOS technology. Based on the introduction of the basic principle of delay circuit and the comparison of various delay circuit structures, the active delay circuit with gm-C structure is adopted in this paper, and the high performance SiGeHBT transistor is used as input tube, which improves the working frequency range of delay circuit. The delay circuit changes the delay time by adjusting the variable capacitance, and extends the circuit bandwidth by using the inductance peaking and emitter negative feedback technology. In order to reduce the reflection of the signal at the input and output ports, the designed matching circuit can ensure that the reflection coefficient of the delay circuit is less than -10 dB in the working frequency band. The delay locking loop in this paper can adjust the delay time of the delay circuit and keep the delay time constant at different processing angles, temperatures and voltages. The delay locking loop consists of a delay circuit, a multiplier and a V / I converter. The delay locking loop has the function of negative feedback regulation, which can guarantee the total delay time of the delay circuit to be 1/4 clock cycle in the loop. In order to reduce the phase error introduced by each module in the loop, an all-symmetric four-quadrant multiplier and a low-offset V / P I converter are designed, which can effectively improve the locking accuracy of the delay locking loop. The size of the designed chip is 500 渭 m 脳 800 渭 m. The test results show that the average delay time of single-stage delay circuit can be kept around 8ps within the operating frequency range of 4-12GHz, and when the control voltage changes, The delay time of single stage delay circuit can be changed from 7.3ps to 8.4 ps. A matching circuit is added to the input and output of the delay circuit to ensure that the reflection coefficients of S11 and S22 are less than -10 dB in 0.2-25GHz. When the frequency of the clock signal is changed, the control voltage generated by the delay locking loop can adjust the delay time of the delay circuit and improve the delay stability of the delay circuit. The design of delay cell and delay locking loop in this paper is of great significance to the design and application of low delay broadband delay circuit in the future.
【学位授予单位】:东南大学
【学位级别】:硕士
【学位授予年份】:2017
【分类号】:TN432
【参考文献】
相关期刊论文 前1条
1 洪志良;全MOS管组成的模拟四象限CMOS乘法器[J];固体电子学研究与进展;1995年04期
,本文编号:1941825
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