基于增益单元的抗辐射嵌入式存储器研究

发布时间：2018-01-10 15:09

  本文关键词：基于增益单元的抗辐射嵌入式存储器研究　出处：《华中科技大学》2016年博士论文　论文类型：学位论文

  更多相关文章： 抗辐射 嵌入式存储器 增益单元 自适应刷新 刷新周期 刷新功耗 隐式刷新

【摘要】：在空间环境中,高能粒子入射到半导体材料中产生大量电子-空穴对,引发总剂量效应和单粒子效应,使电子系统时刻面临辐射效应的威胁。单粒子效应使电子系统中的数据发生错误,导致控制系统和整个航天器发生故障。在航天器的电子系统中,占据芯片大部分面积的嵌入式存储器受单粒子效应的影响最为严重,是最脆弱的器件。当前基于6T SRAM单元的嵌入式存储器的抗辐射加固普遍会导致存储器面积的大幅增加,最终使得电子系统的面积和成本大幅增加。另一方面,由于6T SRAM单元读写操作的比率特性,其数据稳定性随工艺的发展而迅速下降。传统的基于6T SRAM单元的抗辐射嵌入式存储器存在明显的不足。本文基于增益单元结构,对抗辐射嵌入式存储器进行了深入研究,取得的主要成果如下。首先,提出一种基于增益单元的抗总剂量效应(Total Ionizing Dose:TID)和单粒子闩锁(Single Evnet Latchup:SEL)加固的4P eDRAM单元。通过对增益单元的特性分析以及TID效应和SEL效应的原理的分析,提出一种新的抗TID/SEL加固的嵌入式存储单元。对4P eDRAM单元进行了详细的分析,采用高阈值(H-VT)写访问管技术、负字线电压技术(Negative Word Line:NWL),差分结构和电压上拉技术(Voltage Boosting technology:VBT)来改进存储单元的读写性能和数据保持时间。该存储单元与逻辑兼容,可以采用标准CMOS工艺,具有较好的存储性能和较小的存储单元面积。其次,提出双模冗余(Dual-Modular Redundant:DMR)和列向比特间隔(Column Direction Bit-Interleaving:CDBI)相结合的抗单粒子翻转(Single Event Upset:SEU)和多位翻转(Multiple Cell Upset:MCU)的加固技术。通过对4P eDRAM单元的SEU特性和MCU特性的研究,提出采用DMR技术对4P eDRAM单元实现抗DMR加固。研究了DMR加固后的HGC eDRAM单元的MCU特性,提出CDBI技术使HGC eDRAM单元中的二个子单元在物理上隔离,实现抗MCU加固。仿真结果证实,HGC eDRAM单元能够在线性能量传输值(Linear Energy Transfor:LET)为120 MeV·cm2/mg的单粒子效应下,依然能够读出正确的数据,实现良好的抗SEU和MCU性能。对HGC eDRAM单元以及传统的基于6T SRAM单元的抗辐射加固方案进行了对比分析,结果表明HGCeDRAM单元能够实现良好的抗辐射加固性能,同时具有较小的存储单元面积。第三,提出一种降低刷新功耗的自适应刷新周期(Adaptive Refresh Period:ARP)控制系统。研究了HGC eDRAM的静态功耗和刷新功耗,根据温度和访问特性对HGCeDRAM单元数据保持时间的影响,提出一种基于Replica技术的ARP控制系统。采用ARP控制系统,存储器在高温下以较高的频率进行刷新,在低温下以较低的频率进行刷新,降低了HGC eDRAM的刷新功耗。在650C以下温度,相比于传统的固定刷新频率的方法,将刷新功耗降低99.72%。同时,ARP控制系统实现较低的探测误差和较小的探测功耗。最后,提出一种基于分段交错的隐式刷新方法。为了解决传统的刷新方法导致外部访问产生较大的延迟,以及访问带宽可用率下降的问题,提出一种分段交错的隐式刷新方法。分段交错的刷新方法避免了外部访问和内部刷新的冲突,使外部访问能实时进行,降低了刷新周到的访问延迟,同时将访问带宽的可用率提高到100%。提出一种Dual-Port HGC eDRAM存储器,数据带宽增加100%,外部访问与内部刷新不发生冲突,访问带宽的可用率保持100%。针对分段交错的隐式刷新方法完成一行刷新需要二个时钟周期的问题,提出一种快速隐式刷新的方法。将完成整个存储器Bank刷新需要的时钟周期数降低约50%。对采用了隐式刷新方法的HGC eDRAM Bank进行了仿真验证。
[Abstract]:In the space environment, resulting in a large number of electron hole pairs of high-energy particles incident to the semiconductor material, causing effects of total dose and single event effect, the electronic systems always face the threat of radiation effect. The effect of single particle in the electronic system data error, lead to the control system and the whole spacecraft fault in the electronic system of spacecraft. The influence of embedded memory chip, occupy most of the area affected by the single particle effect is most serious, is most vulnerable. The current device based on embedded 6T memory SRAM cell radiation hardening generally leads to a substantial increase in the area of memory, finally makes a substantial increase of electronic system cost and size. On the other hand, because of the ratio characteristics of the 6T SRAM unit of read and write operations, the development of the data process and the rapid decline in stability with the anti radiation. Embedded 6T SRAM based on the traditional unit There are obvious deficiencies. The memory gain cell structure based on embedded memory against radiation is studied, the main results are as follows. First, put forward a total dose effect gain based on unit (Total Ionizing Dose:TID) and single event latch (Single Evnet Latchup:SEL) 4P eDRAM unit. Through the analysis of the principle of reinforcement to gain unit and character analysis of TID effect and SEL effect, put forward a new anti TID/SEL reinforcement embedded storage unit. The 4P eDRAM unit was analyzed in detail, the high threshold value (H-VT) write access tube technology, negative word line voltage technology (Negative Word Line:NWL), poor pull technology the structure and voltage (Voltage Boosting technology:VBT) to improve the memory read and write performance and data retention time. The storage unit and logic can compatible with the standard CMOS process, with The storage unit area has good storage performance and smaller. Secondly, the dual redundancy (Dual-Modular Redundant:DMR) and a column to a bit interval (Column Direction Bit-Interleaving:CDBI) the combination of SEU (Single Event Upset:SEU) and (Multiple Cell Upset:MCU) multi flip reinforcement technology. Through the study of SEU characteristics and MCU characteristics of 4P the eDRAM unit, proposed the anti DMR reinforcement of 4P eDRAM unit using DMR technology. On the MCU characteristics of HGC eDRAM DMR unit after reinforcement, proposed CDBI technology make two sub unit of HGC eDRAM unit in isolation in physics, anti MCU reinforcement. The simulation results show that the HGC eDRAM unit to linear energy the transmission value (Linear Energy Transfor:LET) is a single particle effect of 120 MeV - cm2/mg, still be able to read the correct data, SEU and MCU to achieve good resistance on HGC eDRA. The M unit and the traditional anti radiation reinforcement scheme of 6T based on SRAM elements were analyzed. The results show that the HGCeDRAM unit can achieve good radiation resistant performance, storage unit area and has smaller. Third, proposed a new adaptive reduced brush cycle refresh power (Adaptive Refresh Period:ARP) control system of static power. HGC eDRAM and refresh power, according to the effect of temperature and holding time on the data access characteristics of HGCeDRAM unit, a ARP control system based on Replica technology. Using ARP control system, storage at high temperature with high frequency refresh, refresh at lower frequencies at low temperatures, reduced power consumption refresh HGC eDRAM. Under 650C temperature, fixed refresh rate compared to the traditional, will refresh the power consumption is reduced by 99.72%. at the same time, the realization of ARP control system is relatively low The detection power detection error and smaller. Finally, put forward a kind of implicit refresh method based on piecewise staggered. In order to solve the traditional method to refresh external access to large delay, and access to available bandwidth of the rate of decline, this paper presents a kind of implicit piecewise staggered refresh method. The method avoids the cross segment refresh the external and internal refresh access conflict, so that the external real-time access, reduce the refresh and thoughtful access latency, improve the availability and access bandwidth to 100%. a Dual-Port HGC eDRAM memory, according to the number of bandwidth increases 100%, the external and internal refresh access are not in conflict, the availability of access bandwidth for 100%. implicit piecewise staggered refresh method to complete a refresh requires two clock cycles, a method is proposed to fast hidden refresh. Will complete the entire storage Ban The number of clock cycles required for the K refresh is reduced by about 50%. for the simulation verification of the HGC eDRAM Bank using the implicit refresh method.

【学位授予单位】：华中科技大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TP333
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本文编号：1405731