低电压CMOS分数分频锁相环频率综合器关键技术研究

发布时间：2018-04-05 14:38

本文选题：锁相环　切入点：分数分频频率综合器　出处：《西安电子科技大学》2016年博士论文

【摘要】：锁相环频率综合器是无线通信系统中的关键模块,其具有输出信号频谱纯净、功耗低、实现和应用成本低等特点,因此被广泛应用在射频前端无线收发机中为发射端基带信号上变频或接收端射频信号下变频提供本振信号。此外,无线收发机中的通信信道选择也是由频率综合器来完成的。随着当前无线通信的快速发展和智能便携终端的广泛普及,采用先进CMOS工艺制造的全集成收发机SOC已经成为低成本无线设备的主流选择,并且正在向更低的功耗,更高的集成度、更多的通信模式和功能方向不断迈进。因此必须设计具有宽输出频率范围的低功耗、低相位噪声锁相环频率综合器来适应以上的趋势。本文围绕低电压锁相环频率综合器设计所面对的挑战展开,着重对其中关键模块的电路设计进行了研究。本文的主要工作包含以下几个方面:首先研究了锁相环频率综合器的系统设计方法,通过建立锁相环的S域线性时不变(LTI)系统模型来分析和研究环路的动态特性和稳定性,并且以之为指导来设计高阶环路滤波器。此外,通过推导环路内部各模块噪声转换为相位噪声的传递函数,得到了整数分频和分数分频锁相环的相位噪声分析模型,运用此模型可以在系统顶层设计时就对相位噪声进行优化。低电压条件下传统B类VCO的性能会发生严重退化,而在理论上更适合低电压应用的C类VCO却存在可靠性差、振幅和相位噪声对PVT变化和频率调谐过程敏感等问题。为了解决这些问题,本文提出了一种新的C类VCO结构,包含两个控制环路。一个低频共模信号反馈环路用于将交叉耦合对晶体管偏置在C类工作模式,另一个振幅信号反馈环路用于控制振幅并使之稳定。得益于创新的双反馈环路设计,本文提出的VCO能在起振时产生时变的谐振腔偏置电流,从而具有与传统B类VCO相似的启动过程,在可靠性方面获得了显著的提升。此外,该新型VCO还具备振幅调节功能,能在实际应用根据特定需求来设置最佳工作点,实现功耗和相位噪声指标的优化。为了验证新VCO结构的有效性,本文采用0.18μm CMOS工艺设计并实现了一款双环反馈C类VCO原型芯片。测试结果显示:该原型VCO的频率调谐范围为4.55-5.16GHz,在1.5V电源电压下芯片功耗为2.78mW。当工作在5GHz振荡频率时,距离载波频率1MHz频率偏移处的相位噪声是-123.3dBc/Hz,对应得到的FOM值为-192.8dBc/Hz。本文针对低电压应用提出了一种输出电流可编程高性能电荷泵。该电荷泵由两个子电荷泵组成,其中每个子电荷泵利用反馈控制和复制偏置技术来保证各自的输出电流具有精确的匹配性。在宽输出电压范围内,这两个子电荷泵的输出电流被设计成具有相反的变化趋势,因此利用电流求和结构就能使两者的变化相互补偿,从而得到恒定的总输出电流。该电荷泵采用0.13μm CMOS工艺设计,能编程输出50μA到1.55mA的电流,并以50μA为调节步进。在1.2V电源电压下,输出电压从0.1V变化到1.05V时,后仿结果显示该电荷泵输出总电流的失配率和变化率不超过0.15%和5%。近乎理想的电流匹配特性能将参考杂散减小到尽可能低的水平,同时还能将电荷泵引起的环路非线性降到最低,而良好的输出电流稳定性则有助于环路带宽保持恒定。关于频率综合器中其他关键模块的研究,例如鉴频鉴相器、数字ΔΣ调制器、可编程分频器、双模预分频器等,在本文的相关章节做了详细讨论。最后,采用0.13μm CMOS工艺设计并实现了一款分数分频锁相环频率综合器原型芯片,面积为1.68mm2。其中VCO采用本文提出的新型结构,频率调谐范围是4.4-5.4GHz。频率综合器输出的正交I/Q信号是VCO输出信号的二分频结果,能覆盖2.2GHz到2.7GHz的频率范围。该锁相环频率综合器采用MASH1-1-1结构的数字ΔΣ调制器来实现分数分频功能。测试结果显示:在1.2V的电源电压下,频率综合器原型芯片的总功耗为12.5mW,在要求的输出频率范围内,距离载波1MHz频率偏移处的相位噪声不超过-122dBc/Hz,而且参考杂散和分数杂散均未超过-70dBc。
[Abstract]:The PLL frequency synthesizer is the key module in wireless communication system, its output signal spectrum purity, low power consumption, realization and application of low cost, so it is widely used of baseband signal frequency or receiving RF signal conversion for local oscillator signal in the RF front-end of wireless transceiver. In addition, the communication channel select the wireless transceiver is accomplished by frequency synthesizer. With the popularization of the rapid development of wireless communication and intelligent mobile terminal, using advanced manufacturing technology to complete CMOS transceiver SOC has become the mainstream of low cost wireless equipment selection, and is to lower power consumption, higher integration, communication mode the function and direction of more forward. So it must be low power design with a wide range of output frequency, low phase noise PLL frequency synthesizer to adapt to The trend. This paper focuses on the design of low voltage phase locked loop frequency synthesizer challenge, focuses on the circuit design of the key modules were studied. The main work of this paper includes the following aspects: firstly, research the system design method of PLL frequency synthesizer, unchanged through the S domain established a linear phase locked loop when (LTI) system model to analyze and study the loop dynamics and stability, and in order to guide the design of high order loop filter. In addition, through the derivation of each module within the loop noise transfer function for phase noise, the phase noise of the integer frequency and fractional PLL analysis model, using this model in the top-level design is to optimize the phase noise. The traditional class B under the condition of low voltage VCO performance will be degraded seriously, and in theory should be more suitable for low voltage The C class VCO has poor reliability, the amplitude and phase noise on the PVT change and frequency tuning process sensitive. In order to solve these problems, this paper proposes a new C VCO structure contains two control loop. A low frequency common mode signal feedback loop for cross coupled transistor bias in C type of work mode, another feedback loop is used to control the amplitude of signal amplitude and make it stable. Thanks to the innovative design of double feedback loop, the proposed VCO can generate time-varying bias current of resonant cavity in vibration, and thus has the traditional class B VCO boot process similar to that obtained significant improvement the reliability of the model. In addition, VCO also has amplitude adjustment function, can be set according to the specific needs of the best work in the practical application, realize the optimization of power and phase noise index. In order to verify the validity of the new VCO structure, This paper uses 0.18 m CMOS process to design and realize a double loop feedback class C VCO prototype. The test results show that the frequency tuning range of the prototype of VCO is 4.55-5.16GHz, the supply voltage of 1.5V chip power consumption is 2.78mW. when operating in the 5GHz oscillation frequency, the phase noise at the carrier frequency 1MHz frequency offset distance is -123.3dBc/Hz corresponding, the FOM value obtained for -192.8dBc/Hz. based on Low Voltage Applications presents a high performance programmable current charge pump. The charge pump consists of two charge pump, wherein each sub charge pump using feedback control and replication bias technology to ensure the output current with their matching accuracy. In the wide output voltage within the range of the output current of the two sub charge pump is designed to have the opposite trend, the current and the structure can make the change from mutual compensation The total output current is constant. 0.13 m CMOS process is adopted in the design of the charge pump can output current programming 50 A to 1.55mA, and 50 A for adjusting step. Under the 1.2V supply voltage, the output voltage changes from 0.1V to 1.05V, simulation results show that the charge pump output the current mismatch rate and the rate of change is less than 0.15% 5%. and the current nearly ideal matching characteristics can be reduced to the reference spur as low as possible, but also will cause the nonlinear loop charge pump to a minimum, while the output current stability is helpful to maintain constant loop bandwidth on the other. The key module in the frequency synthesizer, such as PFD, digital modulator, programmable divider, prescaler, discussed in detail in the paper. Finally, using 0.13 m CMOS technology to design and realize a fraction Frequency PLL frequency synthesizer prototype chip, new structure area of 1.68mm2. where VCO is proposed, the frequency tuning range is I/Q 4.4-5.4GHz. orthogonal frequency synthesizer output signal is the output signal of VCO two frequency, frequency range can cover the 2.2GHz to 2.7GHz. The PLL frequency synthesizer using digital delta sigma modulator MASH1-1-1 the structure to achieve the fractional frequency function. The results showed that: in the power supply voltage of 1.2V, the total power consumption of the frequency synthesizer prototype chip is 12.5mW, the output in the specified frequency range, phase noise of carrier frequency distance 1MHz offset is less than -122dBc/Hz, and the reference spur and fractional spurs did not exceed -70dBc.

【学位授予单位】：西安电子科技大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN74

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