高性能带通∑△模数转换器芯片研究与实现

发布时间：2018-08-02 17:59

【摘要】：近年来,高精度电容式加速度计片上系统(SoC)将微机械传感器与外围电路相集成,进一步压缩体积,节省成本,并具有分辨率高、噪声低、温漂系数小、功耗低等优点,在航空航天、国防军工、地震勘测等尖端领域起着重要作用,具有广阔的发展前景,已成为研究热点。在加速度计SoC中,为了将传感器采集到的加速度信号完整地提供给数字电路进行数字信号处理,必须先通过高精度的模数转换器(ADC)将传感器输出的模拟信号转换为数字信号。然而,在目前的许多研究中模数转换器已成为限制该系统精度的瓶颈所在。因此设计并实现适用于微机械加速度计的高精度专用模数转换器芯片具有非常重要的意义。Sigma Delta调制技术利用过采样和噪声整形,无需精准的模拟元件即可实现高分辨率,是在CMOS工艺下实现高精度低功耗模数转换的最佳途径。低通型Σ△ADC可以在低频段(0-20KHz)实现18位或更高的转换精度。然而,为消除低频闪烁噪声的影响,电容式微机械加速度计将4KHz带宽的加速度信号调制到100KHz-200KHz频段,从而超出了传统低通Σ△ADC的信号处理范围,而其他高频率的奈奎斯特型ADC又难以达到足够的精度。综合考虑转换精度、功耗和电路复杂度,带通型Σ△ADC更加适用于高精度电容式微机械加速度计的应用。目前国内外已有关于带通Σ△调制技术的研究多集中在无线通信领域,关于微机械传感器应用领域的研究较少,更鲜有实际流片的测试结果。在此背景下,本文研究并设计实现了应用于微机械加速度计SoC的高精度、低功耗带通sigma-delta模数转换器。论文主要工作及创新点包括:系统地分析了不同类型和结构Σ△调制器的差异,为达到高转换精度并保证高阶Σ△调制器的环路稳定性,首次提出将单环前馈结构应用于高阶带通Σ△调制器,并对该调制器的稳定性进行了研究,给出具有实用性的稳定条件。对调制器电路中的各种非理想因素进行理论分析计算,根据系统仿真结果完成了带通∑△调制器的电路设计、版图设计,进行了大量后仿真验证和版图优化。针对带通Σ△调制器输出信号中包含的大量带外噪声,设计了硬件节省的多级数字滤波器,避免在应用过程中带外噪声混叠到带内。基于0.18μm 1P6M Mixed-signal CMOS工艺,设计并实现了带有6阶1比特量化调制器的世上首款可工作于100KHz-200KHz频段的高精度带通Σ△ADC芯片。单比特量化ΣA ADC裸片面积5mm2(包含IO),模拟部分采用3.3V电源电压,数字部分采用1.8V电源电压。测试结果表明,ADC芯片在4KHz信号带宽内功耗5.8mW,可以达到90dB信噪失真比,96dB动态范围。两种定义的综合品质因数FOM分别达到156dB和23.3pJ/step,与其他应用领域的带通ADC测试结果对比,本文的FOM均处于国际先进水平。为进一步提高Σ△调制器在低过采样率条件下的转换精度,本文在单比特量化调制器基础上进行改进,又设计了一款单环前馈6阶4比特量化带通Σ△调制器,并给出稳定条件。在系统仿真验证中,分析了多比特量化调制器内反馈DAC电容失配对调制器整体线性度的影响,首次提出该反馈DAC非线性模型,设计了动态元件匹配电路,减小了该电容失配引起的非线性。完成了带有4比特量化调制器的ΣAADC的电路设计、版图设计、后仿真验证。4比特量化Σ△ ADC裸片面积4mm2(包含IO),在1.8V/3.3V电源电压下功耗为6.5mW,后仿真结果表明在4KHz带宽内信噪失真比为96dB,动态范围102dB。与第一款的后仿值相比,转换精度提高了 3dB,满足了应用需求。
[Abstract]:In recent years, the high precision capacitive accelerometer on chip system (SoC) integrates the micromechanical sensor with the peripheral circuit, further compresses the volume, saves the cost, and has the advantages of high resolution, low noise, low temperature drift coefficient, low power consumption and so on. It plays an important role in the fields of aerospace, national defense military work, seismic survey and so on. In the accelerometer SoC, in order to integrate the acceleration signals collected by the sensor to digital circuits for digital signal processing, a high precision analog to digital converter (ADC) must be used to convert the analog signal output from the sensor to digital signal. The converter has become the bottleneck to limit the precision of the system. Therefore, it is very important to design and implement a high precision special analog to digital converter chip suitable for micromachined accelerometers..Sigma Delta modulation technology uses over sampling and noise shaping, without precise analog components, it can achieve high resolution. It is under the CMOS process. The best way to achieve high precision and low power analog conversion. Low pass sigma delta ADC can achieve 18 bit or higher conversion accuracy at low frequency (0-20KHz). However, in order to eliminate the influence of low frequency scintillation noise, the capacitive micromachined accelerometer modulates the acceleration signal of 4KHz bandwidth to the 100KHz-200KHz band, which is beyond the traditional low pass sigma delta ADC. The range of signal processing, while other high frequency Nyquist type ADC is difficult to achieve enough precision. Considering the conversion precision, power and circuit complexity, the band-pass sigma delta ADC is more suitable for the application of high precision capacitive micromachined accelerometers. At present, the research on the bandpass sigma delta modulation technology has been concentrated in the world at present. In the field of line communication, there are few studies on the application of micromechanical sensors, and more of the test results of actual flow sheets. In this context, a high precision and low power bandpass sigma-delta analog to digital converter applied to the micromachined accelerometer SoC is studied and designed. The main work and innovation points of this paper are as follows: systematic analysis In order to achieve high conversion precision and guarantee the stability of high order sigma delta modulator, the single loop feedforward structure is first applied to the high order bandpass sigma delta modulator, and the stability of the modulator is studied, and the stability conditions of the modulator are given. The ideal factors are theoretically analyzed and calculated. According to the simulation results, the circuit design of the bandpass sigma delta modulator is completed and the layout is designed. A large number of post simulation verification and layout optimization are carried out. A multilevel digital filter is designed for the hardware saving in the output signal of the bandpass Sigma delta modulator, which avoids the application of the multilevel digital filter. The outside band noise is mixed into the band. Based on the 0.18 m 1P6M Mixed-signal CMOS process, the first high precision bandpass sigma delta ADC chip with the 6 order 1 bit quantization modulator is designed and implemented. The single specific quantization Sigma A ADC bare area 5mm2 (including IO), the analog part uses the 3.3V power supply voltage, the digital part. 1.8V power supply voltage is used. The test results show that ADC chip can consume 5.8mW in 4KHz signal bandwidth, and can achieve 90dB signal to noise distortion ratio and 96dB dynamic range. The two defined comprehensive quality factor FOM reaches 156dB and 23.3pJ/step respectively. Compared with other applications, the FOM of this paper is in the international advanced level. In order to further improve the conversion precision of the sigma delta modulator under low oversampling rate, this paper improves on the basis of a single quantization modulator. A single loop feedforward 6 order 4 bit quantization band pass sigma delta modulator is designed, and the stability conditions are given. In the system simulation verification, the feedback DAC capacitance in the multi bit quantization modulator is analyzed. The feedback DAC nonlinear model is proposed for the first time, and the dynamic component matching circuit is designed for the first time. The nonlinearity caused by the capacitor mismatch is reduced. The circuit design, layout design with 4 bit quantization modulator, the layout design, and the post simulation verification of the.4 bit quantization sigma delta ADC bare area 4mm2 (including IO) are completed. The power consumption is 6.5mW under the 1.8V/3.3V power supply. The simulation results show that the signal to noise distortion ratio in 4KHz bandwidth is 96dB, the dynamic range 102dB. is compared with the first model, and the conversion precision is improved by 3dB, and the application needs are satisfied.
【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2017
【分类号】：TN792;TN761

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