550V厚膜SOI-LIGBT器件可靠性研究

发布时间:2019-06-24 19:30
【摘要】:厚膜绝缘体上硅(SOI)工艺具有隔离性能好、抗辐射能力强和寄生参数小等优点,而横向绝缘栅极极型晶体管(LIGBT)器件具有击穿电压高、电流能力强及可集成的特点,因此厚膜SOI-LIGBT器件受到了功率集成电路的青睐,在智能家电、电动汽车、工业控制和显示驱动等领域有着广泛的应用,成为未来智能功率集成电路的核心元件之一。然而,厚膜SOI-LIGBT器件实际工作过程中的外部静电冲击、高工作电压、大电流密度、功耗带来的自热效应等问题导致器件在实际工作过程中面临着严峻的可靠性问题。这些可靠性问题决定了芯片的可靠性等级和应用范围,限制了智能功率集成电路的进一步发展。因此,本文针对厚膜SOI-LIGBT器件最为关键的静电泄放(ESD)冲击、热载流子(HCI)损伤和闩锁效应(Latch-up)三个方面的可靠性问题进行了系统的研究。该研究对厚膜SOI-LIGBT器件和相应功率集成电路的可靠性评估具有实际参考意义,对厚膜SOI-LIGBT的可靠性优化设计提供了理论依据和指导。本文的主要工作和创新如下:1、研究了厚膜SOI-LIGBT器件在ESD冲击下栅极耦合阶段、电压回滞阶段和电压维持阶段的响应特性,揭示了器件在ESD冲击下的失效机理。基于响应特性和失效机理的研究建立了厚膜SOI-LIGBT器件的ESD响应特性的行为模型,模型误差在10%以内。在此基础上,提出了一种高鲁棒性的栅电极分段接地结构SOI-LIGBT器件。该器件在损失一定电流能力(5-10%)的情况下显著提升了器件的ESD能力(大于20%)。2、揭示了厚膜SOI-LIGBT器件的HCI退化机理,并指出漂移区的损伤对厚膜SOI-LIGBT性能退化几乎没有影响。研究发现,器件的最坏HCI应力为高栅极电压应力,最坏应力下的HCI退化主要由器件沟道区的界面态产生和热电子注入主导。研究了器件开关转换阶段的损伤在整个应力过程中的作用,从而建立了器件在动态应力下的HCI退化寿命模型,模型的最大误差小于7%。3、提出了两种高HCI可靠性的SOI-LIGBT新结构。其中阳极N+环结构可以通过折中器件电流能力的方式有效降低器件的HCI退化,而鸟嘴处带有额外P型区结构器件可以在不影响器件其它性能的情况下显著提升器件的HCI可靠性。4、分析了厚膜SOI-LIGBT器件的闩锁机理。建立了器件中空穴电流的模型,所建空穴电流模型的均方根误差小于1%,最大误差小于3%。进而完成了器件的闩锁电压模型,该模型考虑了温度对器件闩锁安全工作区的影响。5、提出了两种高抗闩锁能力SOI-LIGBT器件结构。其中阴极带有深P型埋层结构器件在损失器件一定电流能力(小于10%)的情况下将器件的闩锁电压提高了60%,而Trench接地结构在不增加任何工艺步骤且不影响器件其它性能的情况下将器件的闩锁电压提高了25%。
[Abstract]:Silicon (SOI) technology on thick film insulators has the advantages of good isolation performance, strong radiation resistance and low parasitic parameters, while transverse insulated gate transistor (LIGBT) devices have the characteristics of high breakdown voltage, strong current ability and integration. Therefore, thick film SOI-LIGBT devices are favored by power integrated circuits and are widely used in intelligent household appliances, electric vehicles, industrial control and display drive. It will become one of the core components of intelligent power integrated circuits in the future. However, the external electrostatic shock, high operating voltage, high current density and self-heating effect caused by power consumption of thick film SOI-LIGBT devices lead to serious reliability problems in the actual working process. These reliability problems determine the reliability level and application range of the chip, and limit the further development of intelligent power integrated circuits. Therefore, the reliability of (ESD) shock, hot carrier (HCI) damage and latch effect (Latch-up), which are the most critical aspects of thick film SOI-LIGBT devices, is systematically studied in this paper. This study has practical reference significance for the reliability evaluation of thick film SOI-LIGBT devices and corresponding power integrated circuits, and provides a theoretical basis and guidance for the reliability optimization design of thick film SOI-LIGBT. The main work and innovations of this paper are as follows: 1. The response characteristics of thick film SOI-LIGBT devices under ESD shock gate coupling stage, voltage lag stage and voltage maintenance stage are studied, and the failure mechanism of the device under ESD shock is revealed. Based on the study of response characteristics and failure mechanism, the behavior model of ESD response characteristics of thick film SOI-LIGBT devices is established, and the model error is less than 10%. On this basis, a highly robust gate segmented grounding structure SOI-LIGBT device is proposed. Under the condition of losing a certain current capacity (5 鈮,

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