基于防伪控制与可验证水印的硬件安全技术研究

发布时间：2018-03-02 03:38

本文关键词： 主动硬件防伪控制物理不可克隆函数有限状态机硬件水印验证 FPGA　出处：《湖南大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着知识产权核可重用技术在半导体领域中的普遍应用，知识产权核(IP)的盗版、复制和非法过量生产等问题日益严重，给IP核设计者造成了巨大的利益损失，硬件知识产权核(IP)的保护技术的研究正变得愈来愈重要。硬件防伪控制是指一系列方案，它使得IP设计者能对IC的后生产阶段进行有效的控制，从而达到保护IP核和阻止生产厂商非法过量生产目的。硬件水印是一种新兴的IP核保护技术，它通过在IP核中嵌入设计者的标识来对IP核的所有权进行有效标识和认证。硬件防伪控制和硬件水印技术的研究对半导体产业的知识产权核保护具有重要意义。本文着力于研究高安全、低开销的主动IC防伪控制方案和高效比特级硬件水印提取验证方案，主要工作有： (1)针对现有主动硬件防伪控制方案存在的安全性和开销等问题，提出了一种新的基于FSM的主动硬件防伪控制层次型结构。该结构作为额外加入原始FSM的控制锁定部分，通过与物理不可克隆函数进行绑定，，构成一个FSM锁对生产厂商生产出来的每块IC芯片中的IP核进行唯一锁定。每个生产的IC芯片起电时跳到一个固定的起始锁定状态，IC生产厂商只有通过将该IC的唯一PUF标识传回给IP核设计者，才能获得相应唯一的解锁密钥和剩下位数的跳转输入值，以激活IC进行解锁。提出的层次型防伪控制方案首先利用PUF的响应来决定解锁路径，随后利用FSM跳转输入位数以提高其抵抗穷举型攻击的鲁棒性。与现有相关硬件防伪结构相比，提出的结构有更好的安全性以抵抗穷举攻击。本文在Berkeley SIS平台上对两种方案在MCNC基准电路上的面积、时延和功耗开销进行了实验，实验结果表明方案的开销在可以接受的范围。 (2)很多现存的水印技术需要依赖FPGA工具手动从比特文件中提取水印或者需要在比特文件中进行穷举搜索来寻找水印，造成了水印验证的低效性。本文提出了一种使用FPGA中LUT单元内容提取的方法来对比特级水印进行有效地提取验证，从而达到高效验证IP所有权的目的。该方法通过对FPGA中查找表内容在比特文件中的存储位置的分析来从比特文件中提取水印，提取出的各水印部分再进行重新组合后解密为签名，以此使IP核的所有权得到迅速和有效地验证。
[Abstract]:With the widespread application of IPR in semiconductor field, the problems of IP piracy, reproduction and illegal overproduction are becoming more and more serious, which has caused huge loss of benefits to IP core designers. Hardware anti-counterfeiting control refers to a series of schemes, which enable IP designers to effectively control the post-production stage of IC. In order to protect the IP core and prevent the manufacturers from illegally overproducing, the hardware watermark is a new IP core protection technology. It can effectively identify and authenticate the ownership of IP core by embedding the designer's logo in the IP core. The research of hardware anti-counterfeiting control and hardware watermarking technology is of great significance to the intellectual property core protection of semiconductor industry. This paper focuses on the study of high security, The low cost active IC anti-counterfeiting control scheme and the high efficiency hardware watermark extraction and verification scheme, the main work is as follows:. 1) aiming at the security and overhead problems existing in the existing active hardware anti-counterfeiting control schemes, a new active hardware anti-counterfeiting control hierarchy based on FSM is proposed, which is used as a locking part of the active hardware anti-counterfeiting control scheme with the addition of the original FSM. By binding to physically noncloned functions, A FSM lock is formed to uniquely lock the IP core in each IC chip produced by the manufacturer. Each IC chip is switched on to a fixed initial locking state. An PUF ID is returned to the IP core designer, In order to obtain the corresponding unique unlock key and the jump input value of the remaining digits to activate the IC to unlock, the hierarchical anti-counterfeiting control scheme first uses the response of PUF to determine the unlock path. Then the FSM jump input bits are used to improve its robustness against exhaustive attacks. Compared with the existing hardware anti-counterfeiting architecture, The proposed structure has better security against exhaustive attacks. In this paper, the area, delay and power overhead of the two schemes in the MCNC reference circuit are tested on the Berkeley SIS platform. The experimental results show that the cost of the scheme is within an acceptable range. Many existing watermarking technologies need to rely on FPGA tools to manually extract the watermark from the bit file or search through the bit file to find the watermark. In this paper, a method of extracting the content of LUT unit in FPGA is proposed to compare the high level watermark and verify it effectively. In order to verify IP ownership efficiently, this method extracts watermark from bit files by analyzing the storage location of table contents in bit files in FPGA. The extracted watermarks are recombined and decrypted as signatures, so that the ownership of IP cores can be verified quickly and effectively.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP309

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