在FPGA上构建SOA架构并实现AVS编码器

发布时间：2018-03-11 18:10

本文选题：AVS编码器　切入点：FPGA　出处：《太原理工大学》2013年硕士论文　论文类型：学位论文

【摘要】：AVS标准是中国数字音视频编解码技术标准工作组制定的具有自主知识产权的数字音视频编码标准。该标准具有较高的编码效率,达到了国际先进水平,是高清数字电视、网络电视、视频通信等重大音视频应用采用的基础标准,并于2006年正式被批准为新一代音视频编码国家标准。目前,AVS已经被联通采用作IPTV标准,进入产业化推广阶段。AVS标准采用了一系列先进技术,兼顾了处理速度和复杂度两方面的限制,但是编码压缩处理数据量大,运算复杂度仍然很高。FPGA具有较高的性能和灵活性,高速的并行运算速度和丰富的寄存器资源能够实现复杂算法的快速处理,是实现AVS编码器的最佳选择之一。AVS编码处理的数据量大,运算复杂度高,同时为了达到实时编码的要求,需要很快的运算速度。本文提出一种新型架构—FPGA上的面向服务架构(SOA),并用于实现AVS编码器。根据以太网传输的特点,设计了片内只写总线(BoW)以及基于BoW上的消息访问机制,并基于此提出实现BoW的网络拓扑结构。只写总线BoW的网络拓扑结构简单,它由一个主处理器节点(定序器)和若干从处理器节点(原子构件)构成,节点通过统一节点接口(UNI)挂接到总线上,降低了原子构件引脚互连的复杂性。提出并设计实现了一种定序器引擎控制流程的执行顺序,节点之间的互连采用基于BoW总线的消息传递机制,通信协议简单。以此为基础,本文在FPGA上实现了AVS编码器关键算法,包括帧内预测、残差/重构、DCT/IDCT变换、量化/反量化和熵编码。利用FPGA开发工具,对各算法模块进行仿真验证,保证了算法功能的正确性。根据编码算法的特点,将AVS编码器的关键算法分为四个功能模块,各功能模块封装成基于消息访问的原子构件,包括图像采集原子构件、预测变换原子构件、编码原子构件和码流拼接原子构件。为了提高数据处理的速度,各功能模块采用高度并行算法和流水线设计方法进行优化。为了进一步提高编码速度,本文采用总线上重复部署多个原子构件、多个流程并行执行的方式,从而实现高分辨率图像的实时编码。通过ISE综合与ModelSim仿真,最高时钟频率可达130MHz。采用100MHz的系统时钟,在Virtex-5平台上可实现D1分辨率Ⅰ帧图像的实时编码。将实时编码的码流通过以太网传输系统发送给客户端,经解码器解码和播放器显示,验证了AVS编码器的实时编码能力。
[Abstract]:The AVS standard is China digital audio and video coding standard working group to develop with independent intellectual property rights of digital audio and video encoding standard. This standard has higher encoding efficiency, reached the international advanced level, high-definition digital TV, Internet TV, video communication using basic standard and other major audio and video applications, and in 2006 was officially approved for a new generation of audio and video encoding standards. At present, AVS has been adopted as the standard IPTV Unicom, entered the stage of industrialization of.AVS standard adopts a series of advanced technology, the processing speed and the complexity of the two aspects, but the large number of data compression encoding, the computational complexity is still high.FPGA has high performance and flexibility, fast processing speed to realize complex algorithm parallel computing speed and rich resources to register, which is the best choice for the realization of AVS encoder Choose one of the.AVS encoding processing of large amount of data, high computational complexity, at the same time in order to achieve real-time encoding requirements, need fast computation speed. This paper presents a new architecture of FPGA Service Oriented Architecture (SOA), and for the realization of AVS encoder. According to the characteristics of Ethernet transmission design, write only the on-chip bus (BoW) and BoW based message access mechanism, and put forward the implementation of BoW network topology based on the network topology. Just write simple BoW bus, which consists of a main processor node (sequencer) and a plurality of processor nodes (from atomic components), through a unified interface node node (UNI) attached to the bus, reducing the complexity of atomic components pin interconnection. We designed and implemented a sequencer engine control the execution order of the interconnections between nodes using the transmission mechanism of BoW bus based message pass A simple letter agreement. On this basis, the paper implements the key algorithm of AVS encoder based on FPGA, including intra prediction, residual / reconstruction, DCT/IDCT transform, quantization and inverse quantization and entropy encoding. The use of FPGA development tools, the simulation of the algorithm module, to ensure the correctness of the algorithm. According to the characteristics of the encoding algorithm the key algorithm of AVS encoder is divided into four functional modules, each module is encapsulated into atomic components based on message access, including image acquisition atomic components, prediction transform atomic components, encoding atomic components and bitstream splicing atomic components. In order to improve the speed of data processing, each function module adopts a highly parallel algorithm and pipelining design the method was optimized. In order to further improve the encoding speed, this paper adopts the bus to repeat the deployment of multiple atomic components, multi process parallel execution mode, in order to achieve high resolution Real time image encoding rate. Through ISE and ModelSim simulation, the maximum clock frequency is up to 130MHz. using the 100MHz system clock, on the Virtex-5 platform can realize real-time encoding of D1 resolution frames. The real-time encoding bit stream transmitted through Ethernet transmission system to the client, the decoder and player to display, verify the real-time encoding the ability of AVS encoder.

【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN919.81

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