FMC系列采集模块及接口逻辑设计

发布时间：2018-04-29 11:53

本文选题：高速数据采集 + FMC　；参考：《电子科技大学》2013年硕士论文

【摘要】：数据采集作为通信技术的重要环节，在通信技术迅猛发展的同时，对数据采集系统的性能要求越来越高，可以说在高速高精度的前提下，高密度、高集成、可扩展兼容是数据采集系统今后的发展趋势之一。本文设计的FMC（FPGA Mezzanine Card）系列采集模块正是迎合了当今数据采集系统的发展趋势，以灵活可扩展的方式解决宽带信号的捕获、以高度集成的体系结构解决电子系统的嵌入式测试为目标，利用FMC VITA-57标准协议，在标准有限面积内，设计实现了一种具有高集成、高密度、可扩展兼容等特点的高速高精度采集模块。 FMC系列采集模块分为FMC5212（双通道500MSPS/12bits）和FMC4214（双通道400MSPS/14bits），两款产品分别采用AD芯片ADS5463和ADS5474，时钟芯片AD9517-3分别为其提供所需的采样时钟来完成AD转换。模块的兼容性设计方面，在接口逻辑中设计了识别功能来对FMC身份进行识别与验证；为了保护模块设计及其逻辑代码的知识产权，设计了加密防拷贝模块来对FMC接口逻辑进行软件保护；针对高密度、高度集成所导致的模块温度高、电源及信号完整性问题，文中通过对系统功耗和温度，以及串扰与轨道塌陷等问题的详细分析，完成了高效率的电源设计及系统板级设计，，同时设计了状态监控模块对温度及电源加以实时监控。最终对设计结果进行测试与验证，该采集模块SNR、SFDR均达到设计指标，而识别加密模块及状态监控模块均得到验证，满足测试要求，论文主要内容可分为： FMC系列采集模块的硬件设计：AD采样模块、采样时钟模块、触发模块、加密识别模块、温度电压监控模块、电源模块等设计。 FMC系列采集模块接口逻辑的设计：数据解串、配置采样时钟、加密防拷贝、身份识别、监控温度与电压等。对FMC系列FMC5212和FMC4214进行结果测试及功能验证。
[Abstract]:As an important link of communication technology, data acquisition is becoming more and more demanding for the performance of the data acquisition system while the communication technology is developing rapidly. It can be said that high density, high integration and extensible compatibility are one of the future development trends of data acquisition system in the premise of high speed and high precision.
The FMC (FPGA Mezzanine Card) collection module designed in this paper is to cater to the development trend of today's data acquisition system, to solve the acquisition of broadband signal in a flexible and extensible way, and to solve the embedded test of electronic system with a highly integrated architecture, and use the FMC VITA-57 standard protocol in the limited area of the standard. A high speed and high precision acquisition module with high integration, high density, scalability and compatibility is designed and implemented.
The FMC collection module is divided into FMC5212 (dual channel 500MSPS/12bits) and FMC4214 (dual channel 400MSPS/14bits). The two products use AD chip ADS5463 and ADS5474 respectively. The clock chip AD9517-3 respectively provides the required sampling clock to complete the AD conversion. The module is designed with the recognition function to the F in the interface logic. MC identity is identified and verified. In order to protect the intellectual property of module design and its logical code, an encrypted and anti copy module is designed to protect the software of FMC interface logic. High density, high integration results in high module temperature, power and signal integrity problems, through the system power and temperature, and crosstalk in this paper. With the detailed analysis of the track collapse and other problems, the high efficiency power supply design and the system board level design are completed. At the same time, the state monitoring module is designed to monitor the temperature and the power supply in real time. Finally, the design results are tested and verified. The acquisition module SNR, SFDR all achieve the design index, and the recognition encryption module and the state monitoring module are both. To be verified and meet the test requirements.
The main contents of the paper can be divided into:
The hardware design of FMC series acquisition module: AD sampling module, sampling clock module, trigger module, encryption recognition module, temperature and voltage monitoring module, power module and so on.
Design of interface logic for FMC series acquisition module: Data deserializer, configuration sampling clock, encryption and anti copy, identity recognition, monitoring temperature and voltage, etc.
The result test and functional verification of FMC series FMC5212 and FMC4214 are carried out.

【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP274.2

【参考文献】