符合我国标准的UHF RFID阅读器数字基带电路设计

发布时间：2018-05-23 10:19

本文选题：RFID阅读器 + 国标　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：近年来,物联网产业迅速发展,被称为继计算机,互联网之后的第三次信息产业浪潮。作为物联网技术的重要组成部分,RFID技术也得到了广泛关注和迅速发展。其中860-960MHz的超高频RFID技术因具有距离远、速度快、抗干扰能力强等优点,在仓储管理、物流跟踪、自动控制等领域都有应用潜力,具有广阔的市场前景,是目前RFID技术的研究重点。为促进和规范国内RFID产业发展,我国在2013年9月推出《信息技术射频识别800/900MHz空中接口协议》。与国际上该领域的标准协议相比,国标在编码方式,指令定义等方面都具有自主知识产权。本文以将RFID阅读器单芯片化为目标,基于国家标准的空中接口协议,在综合国内外近年来UHF RFID阅读器技术现有的研究成果的基础上,通过对RFID阅读器系统的研究和分析,提出了阅读器系统设计的总体结构,并重点研究了数字基带系统设计与实现。最后将本文设计的UHF RFID阅读器数字基带在FPGA上实现和验证。首先,详细分析了我国新发布的超高频空中接口协议标准,包括物理层的发射链路和接收链路,标签识别层,阅读器和标签通信的指令及通信过程,防碰撞机制等。在此基础上提出UHF RFID阅读器设计的整体结构,并重点研究数字基带系统组成,其功能模块包括发射链路、接收链路、SPI接口和协议处理单元。随后对数字基带的关键模块的原理和设计方法进行分析,确定设计参数。对于其中的成型滤波电路设计,本文将TPP编码和升余弦滤波相结合,同时完成上述功能,本文设计的成型滤波电路具有滤波器阶数,滚降系数等参数灵活可配置、电路开销小、延时短等优点。因标签反向散射信号最大有20%的频偏,为降低误码率,本文采用边沿检测型时钟同步方案实现码元同步。该方案性能满足要求,具有消耗资源少、同步速度快等优点。完成阅读器数字基带系统各电路模块设计,包括发射链路的CRC校验、FIFO、编码和升余弦滤波、希尔伯特滤波、CIC升采样;接收链路的信道滤波、自动增幅控制、时钟同步和译码;SPI接口电路和协议处理单元。本文设计的阅读器数字基带电路完成各个模块的功能仿真,采用Xilinx公司的FPGA芯片Virtex-5系列的XC5VLX110T实现,使用ISE完成电路综合,布局布线等。完成数字基带电路的FPGA平台验证和测试,达到了设计预期目标。
[Abstract]:In recent years, the Internet of things industry has developed rapidly, which is called the third wave of information industry after computer and Internet. As an important part of Internet of things (IoT) technology, RFID technology has also received extensive attention and rapid development. The UHF RFID technology of 860-960MHz has the advantages of long distance, fast speed and strong anti-jamming ability, and has the potential to be applied in the field of warehouse management, logistics tracking, automatic control and so on, so it has a broad market prospect. It is the research focus of RFID technology at present. In order to promote and standardize the development of domestic RFID industry, China launched the Radio Frequency Identification (800/900MHz) Air Interface Protocol in September 2013. Compared with the international standard agreement in this field, national standard has independent intellectual property rights in coding mode, instruction definition and so on. In this paper, the air interface protocol based on national standard is designed to make RFID reader single chip as its target. On the basis of synthesizing the existing research results of UHF RFID reader technology at home and abroad in recent years, the research and analysis of RFID reader system are carried out in this paper. The overall structure of reader system design is put forward, and the design and implementation of digital baseband system are studied. Finally, the digital baseband of the UHF RFID reader designed in this paper is implemented and verified on FPGA. Firstly, the newly issued UHF air interface protocol standards in China are analyzed in detail, including the physical layer's transmitting link and receiving link, label identification layer, the instruction and communication process of reader and tag communication, collision prevention mechanism and so on. On this basis, the whole structure of UHF RFID reader design is proposed, and the digital baseband system is studied. The function module includes transmitting link, receiving link, SPI interface and protocol processing unit. Then, the principle and design method of the key module of digital baseband are analyzed, and the design parameters are determined. For the design of shaping filter circuit, this paper combines TPP coding with raised cosine filter, and accomplishes the above functions. The shaping filter circuit designed in this paper has the parameters such as filter order, roll down coefficient and so on, which can be configured flexibly, and the cost of circuit is small. Short delay, etc. Because the label backscattering signal has a maximum frequency offset of 20%, in order to reduce the bit error rate, the edge detection clock synchronization scheme is used to realize symbol synchronization in this paper. The performance of the scheme meets the requirements, with the advantages of less resource consumption and high synchronization speed. Complete the design of various circuit modules of the digital baseband system of reader, including the CRC check FIFO of the transmission link, the encoding and ascending cosine filtering, the Hilbert filter and CIC up-sampling, the channel filtering of the receiving link, the automatic increase control, Clock synchronization and decoding SPI interface circuit and protocol processing unit. The reader digital baseband circuit designed in this paper is used to realize the function simulation of each module, which is realized by XC5VLX110T of FPGA chip Virtex-5 series of Xilinx company, circuit synthesis, layout and wiring by ISE, etc. The FPGA platform of digital baseband circuit is verified and tested, and the design goal is achieved.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN402;TP391.44

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