基于OR1200的UHF RFID阅读器数字基带处理SoC设计

发布时间：2018-06-06 17:20

本文选题：UHF + RFID阅读器　；参考：《南京航空航天大学》2013年硕士论文

【摘要】：随着集成电路制造工艺的发展、设计工具自动化程度与设计技术的提高，单个芯片上能够集成的电路功能也变得越来越复杂。集成电路由专用集成电路ASIC（Application SpecificIntegrated Circuit）向片上系统SoC（System on Chip）方向发展的形势日趋明显。包含处理器在内的系统级芯片集成技术，可以较好降低系统整体的功耗、面积，提高芯片运行速度，提升芯片性能。目前，基于IP（Intellectual Property，知识产权）核的片上系统设计，是超大规模集成电路设计的核心领域。 RFID（Radio Frequency Identification，射频识别）阅读器是射频识别产品的重要组成部分。相比其他频段，，超高频段的RFID具有以下几个明显的优势：识别距离较远、传输速度高、操作快捷、可实现多目标识别、移动目标识别等。目前，大部分射频识别设备尤其是手持式设备均工作在超高频段。随着超高频RFID设备的大范围使用和技术改进，阅读器的单芯片解决方案已经成为行业发展趋势。数字基带信号处理是阅读器芯片设计的组成部分，将这部分功能采用片上系统的设计方法实现，是完成单芯片阅读器的重要基础。本课题依据ISO18000-6C协议要求，完成RFID阅读器数字基带信号处理的片上系统设计。应用了开源资源网站Opencores.org维护和提供的OpenRisc OR1200处理器内核以及一系列IP核，系统的总线采用OpenRisc所支持的开源片上总线Wishbone，自行设计完成协议处理单元IP核，实现功能包括基带信号PIE编码、FM0解码与CRC-5/CRC-16校验，完成数据的发送与接收，并根据Wishbone总线协议配置相应的设备接口，从而实现基带信号处理IP核设计。片上RAM、PLL等由Quartus II提供的工具生成。硬件采用自上而下的设计方法，完成各个IP核的分析设计和功能仿真，再将各个IP核互联实现硬件设计。搭建系统软件开发所需的GNU工具链环境，编码设计完成硬件系统的启动与应用程序。最终实现阅读器的基带处理SoC系统软硬件设计。系统的验证工作通过Modelsim仿真软件和FPGA开发板实现。
[Abstract]:With the development of IC manufacturing technology, the automation of design tools and the improvement of design technology, the integrated circuit functions on a single chip become more and more complex. The development of integrated circuits from ASIC / ASIC Application specific Integrated Circuit (ASIC) to SoCon system on Chip (SOC) is becoming more and more obvious. The integrated technology of system level chip, including processor, can reduce the power consumption and area of the whole system, improve the speed of the chip and improve the performance of the chip. At present, the on-chip system design based on IP IP intellectual property (IP) core is the core field of VLSI design. RFID Radio Frequency Identification (RFID) reader is an important part of RFID products. Compared with other frequency bands, UHF RFID has the following obvious advantages: the identification distance is long, the transmission speed is high, the operation is fast, and the multi-target identification and moving target identification can be realized. At present, most RFID devices, especially hand-held devices, work in UHF. With the wide use and technical improvement of UHF RFID devices, the single-chip solution of readers has become a trend in the industry. Digital baseband signal processing is an integral part of reader chip design. It is an important foundation to complete single-chip reader by adopting the design method of on-chip system. This subject is based on ISO18000-6C protocol. Complete RFID reader digital baseband signal processing system design. OpenRisc OR1200 processor kernel and a series of IP cores, which are maintained and provided by Opencores.org, are applied. The system bus adopts Wishbone, an open source on-chip bus supported by OpenRisc, to design and complete the protocol processing unit IP core. The realization functions include baseband signal PIE-coding FM0 decoding and CRC-5 / CRC-16 check, data sending and receiving, and configuration of corresponding device interface according to Wishbone bus protocol, so as to realize the design of baseband signal processing IP core. On-chip RAM PLL and so on are generated by tools provided by Quartus II. The hardware adopts the top-down design method to complete the analysis design and function simulation of each IP core, and then interconnect each IP core to realize the hardware design. The GNU toolchain environment is built for the software development of the system, and the hardware system startup and application program are designed and coded. Finally, the hardware and software design of the baseband processing SoC system is realized. The verification of the system is realized by Modelsim simulation software and FPGA development board.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP391.44

【参考文献】