铁路信号应答器系统及其低功耗高可靠性专用芯片的设计研究

发布时间：2018-07-04 13:42

本文选题：应答器 + 读写器　；参考：《浙江大学》2014年博士论文

【摘要】：近年来,我国铁路和城市轨道交通取得了迅猛发展,但是作为其中基础通信的应答器系统设施长期以来严重依赖国外进口。因此,研究具有自主知识产权的高可靠性应答器系统迫在眉睫。目前国内应答器技术正处于起步阶段,本文通过解剖分析国外先进的应答器系统,了解与掌握其功能定义、工作原理及系统方案。一方面,出于功耗、可靠性以及技术保密等原因,国外应答器中的逻辑控制部分是以专用集成电路芯片的形式存在的,这使得试图通过纯反向工程(Reverse Engineering)的方法实现应答器国产化变得颇为困难。另一方面,为了保证应答器中数据的安全性和可维护性,作为应答器数据管理设备的读写器往往由同一应答器厂商配套提供。出于同样原因,难以通过解剖国外产品来指导国产读写器的设计,因此完全自主的研发读写器也成为应答器系统国产化亟待解决的问题。读写器的核心功能是接收应答器发送的FSK信号并解调出报文或序列号数据,用于判断应答器是否正常工作。通常,读写器的工作环境复杂,FSK信号噪声大,因此研究高抗干扰低误码率FSK解调算法是确保读写器能够准确可靠的管理应答器的前提。由于应答器是列车与地面之间数据通信必不可少的安全设备,而应答器逻辑控制专用芯片的可靠性直接影响到整个应答器的可靠性,因此本文将抗干扰的三模冗余(Triple Modular Redundancy, TMR)技术引入到应答器逻辑控制专用芯片的底层设计中以提高芯片的可靠性。为了防止因干扰发生在底层表决器上而导致整个应答器TMR逻辑控制专用芯片工作错误,一般会采用传统的自刷新TMR结构。但是传统的自刷新TMR结构会增加芯片内表决器的数量,从而导致芯片功耗增大。由于应答器是通过电磁耦合技术来获取工作能量的,功耗过大无法满足应答器系统对功耗的严格要求,因此必须设计出符合低功耗要求的TMR逻辑控制专用芯片。本文正是基于以上需求来开展相关设计研究工作的。本文的主要贡献如下： 1、为了使读写器具有高抗干扰性能,本文提出了一种低误码率全数字类相干FSK解调算法,并以专用芯片的形式加以实现,在中芯国际SMIC65nm工艺下完成流片。测试表明,该FSK解调算法误码率和功耗等性能均符合读写器系统要求且优于现有非相干解调算法。基于该算法实现的FSK解调器的品质因数(Figure of Merit, FOM)与最近几年国际高水平期刊和会议上的论文水平相当。相关研究成果在SCI期刊Microelectronics Journal Vol.45, No.6(2014.6)上发表。在此基础上,完成了基于该FSK解调算法的读写器整机方案及其专用芯片的设计与测试,相关研究成果在SCI期刊Journal of Circuits, Systems and Computers, Vol.22, No.9(2013.10)上发表。 2、为了解决现有应答器TMR逻辑控制专用芯片中顶层表决器受干扰会造成整个芯片出错的问题,本文提出了一种可替代的双模表决器(Dual Modular Voter,DMV)方案。采用电路节点注入单粒子瞬态翻转(Single Event Transient, SET)的方式,验证了该DMV是一个完全容错的表决器,不会因受到SET干扰而出错,但代价是功耗略高于传统表决器。为了进一步降低功耗,本文相继提出了基于异或门(XOR)和二选一选择器(MUX)实现的表决器电路新形式,该表决器仅由12个MOS管组成,可作为DMV中的单个表决器使用。鉴于DMV是一个完全容错的低功耗表决器,因此该DMV不仅可用作应答器TMR逻辑控制专用芯片中的顶层表决器,还可替代所有的底层表决器。在CSMC0.5um工艺不同工艺角下仿真结果表明,用一个DMV替代三个底层传统表决器后,至少可以节省61%的表决器功耗。为了便于EDA工具将所设计的DMV自动插入芯片版图中,利用商用软件Siliconsmart完成了DMV的标准单元特征化。在无锡上华CSMC0.5um标准CMOS工艺下完成了一款基于DMV的自刷新TMR逻辑控制专用芯片,其电流仅为0.486mA(小于0.7mA的指标要求)。应用了该芯片的应答器,在保持其它性能指标相当的情况下,整机功耗和启动时间这两项关键性能指标均优于西门子公司的产品。DMV相关研究成果在SCI期刊IEICE Electronics Express, Vol.11, No.4(2014.2)上发表。
[Abstract]:In recent years, China's railway and urban rail transit have developed rapidly, but the infrastructure of the transponder system, as a basic communication system, has long been heavily dependent on foreign imports. Therefore, it is imminent to study the high reliability transponder system with independent intellectual property rights. Anatomic analysis of foreign advanced transponder system, understanding and mastering its function definition, working principle and system scheme. On the one hand, the logic control part of foreign transponder is stored in the form of special integrated circuit chip for reasons such as power consumption, reliability and technology secrecy, which makes the attempt to pass the pure reverse Engineering (Reverse Engi). On the other hand, in order to ensure the security and maintainability of the data in the transponder, the reader and writer of the transponder data management device is often provided by the same transponder vendor. For the same reason, it is difficult to pass the dissection of foreign products to guide the design of the domestic reader and writer for the same reason. Therefore, fully autonomous R & D reader is also an urgent problem to be solved in localization of transponder system.
The core function of the reader and writer is to receive the FSK signal sent by the transponder and to solve the message or serial number data. It is used to judge whether the responder is working properly. Usually, the working environment of the reader is complex and the noise of the FSK signal is large. Therefore, the study of the high anti-interference and low error rate FSK demodulation algorithm is to ensure that the reader can be accurately and reliably managed by the reader. The premise.
Because the transponder is a necessary security device for the data communication between the train and the ground, and the reliability of the transponder logic control special chip directly affects the reliability of the whole transponder, this paper introduces the anti jamming three mode redundancy (Triple Modular Redundancy, TMR) technology to the bottom of the transponder logic control special chip. In order to improve the reliability of the chip in the design, in order to prevent the whole transponder TMR logic control special chip from working due to interference on the underlying voter, the traditional self refresh TMR structure is generally adopted. However, the traditional self refresh TMR structure will increase the number of internal chip voter, resulting in the increase of the chip power consumption. The transponder is through electromagnetic coupling technology to obtain the working energy, and the power consumption is too large to meet the strict requirements of the transponder system for power consumption. Therefore, a TMR logic control special chip which meets the requirements of low power consumption is designed.
This article is based on the above needs to carry out relevant design and research work. The main contributions of this paper are as follows:
1, in order to make the reader with high anti-interference performance, this paper presents a low bit error rate all digital coherent FSK demodulation algorithm, which is implemented in the form of a dedicated chip, and completes the flow sheet under the Central International SMIC65nm process. The test shows that the performance of the FSK demodulation algorithm is in accordance with the reader system requirements and is better than the current reader system. There is an incoherent demodulation algorithm. The FSK demodulator's quality factor (Figure of Merit, FOM) based on this algorithm is equal to the level of papers at high international journals and conferences in recent years. The related research results are published on the SCI Journal Microelectronics Journal Vol.45, No.6 (2014.6). On this basis, the demodulation is completed based on the FSK demodulation. The design and test of the whole program and its dedicated chip for the reader and writer of the law are published on the SCI Journal Journal of Circuits, Systems and Computers, Vol.22, and No.9 (2013.10).
2, in order to solve the problem of the whole chip error caused by the interference of the top layer voter in the existing transponder TMR logic control special chip, this paper proposes an alternative Dual Modular Voter (DMV) scheme. The circuit node is injected into the single particle transient flipping (Single Event Transient, SET), and the DMV is validated to verify the DMV. It is a completely fault-tolerant voting device that does not make errors due to SET interference, but costs a little higher than the traditional voting device. In order to further reduce power consumption, a new form of voter circuit based on XOR and two selector (MUX) is proposed. The voter is composed of only 12 MOS tubes, which can be used as a single DMV. In view of the fact that DMV is a fully fault-tolerant low power voting device, the DMV can be used not only as the top layer voter in the transponder TMR logic control special chip, but also in the substitutes of all the underlying voting devices. The simulation results at different process angles of the CSMC0.5um process show that after a DMV is used to replace the three underlying conventional voting devices, At least 61% of the voting power consumption can be saved. In order to facilitate the EDA tool to automatically insert the designed DMV into the chip layout, the standard unit of DMV is characterized by the commercial software Siliconsmart. A self refreshing TMR logic control special chip based on DMV is completed under the CSMC0.5um standard CMOS technology in Wuxi, with a current of only 0.4. 86mA (less than 0.7mA). With the application of the chip's transponder, the two key performance indicators of the whole machine power and startup time are better than the.DMV related research results of SIEMENS's products in the SCI Journal IEICE Electronics Express, Vol.11, No.4 (2014.2).
【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2014
【分类号】：U284.7

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