AVS-S视频编码器变换量化和熵编码模块的硬件设计
发布时间：2018-07-24 10:07
【摘要】：AVS是我国自主知识产权的音视频编解码标准,由AVS工作组制定。AVS-S是在AVS的基础上发展起来的,主要针对安防监控领域的数字视频编解码标准,可以满足远程视频监控的特殊要求。该标准的提出,不仅推动了我国安防产业的发展,也为我国解决了很多专利壁垒问题,节约了专利费用。本文首先对AVS-S标准进行了深入研究,然后分析和优化了该标准中变换、量化和熵编码模块所采用的算法,最后对这三个模块进行了硬件设计和优化。根据ICT变换的特点,采用1-DICT变换和8×8的转置矩阵实现2-DICT变换；对传统的蝶形算法进行了优化,变换后的系数无需重新排序,降低了变换的复杂度。量化模块中,修改了求解加权量化矩阵的方法,避免了多余中间变量的存储,节省了资源；量化后的系数直接按Zig-Zag扫描的顺序存入缓存,减少了对存储器的访问,节省了编码时间；量化模块支持传统的非加权量化技术和质量可调整的加权量化技术,两种量化技术复用一个缩放量化模块,节约了资源。在熵编码模块中,根据run、level和trans_coeffcient的大小关系,对码表进行了压缩,降低了查表的复杂度。本文采用并行流水线的方式,加快了编码速度。本文采用Verilog HDL语言完成AVS-S编码器中变换、量化和熵编码模块的RTL级电路,采用Synopsys的VCS进行功能验证,采用AVS-S标准参考软件SM2_0.4-v3建立参考模型,将VCS的仿真结果与参考模型的结果进行对比来验证本设计的正确性。在Synopsys的Design Compiler综合工具上进行逻辑综合,结果显示,该设计满足时序要求。最后用Formality形式验证工具对设计进行了形式验证。
[Abstract]:AVS is the standard of audio and video coding and decoding of independent intellectual property rights in China. It was developed by the AVS working group on the basis of AVS, and is mainly aimed at the digital video coding and decoding standard in the field of security and surveillance. It can meet the special requirements of remote video surveillance. The proposal of this standard not only promotes the development of China's security industry, but also solves a lot of patent barriers and saves patent expenses. In this paper, the AVS-S standard is studied deeply, then the algorithms used in the transform, quantization and entropy coding modules are analyzed and optimized. Finally, the hardware design and optimization of the three modules are given. According to the characteristics of ICT transform, 1-DICT transform and 8 脳 8 transpose matrix are used to realize 2-DICT transform, the traditional butterfly algorithm is optimized, the coefficients after transformation need not be reordered, and the complexity of transformation is reduced. In the quantization module, the method of solving the weighted quantization matrix is modified to avoid the storage of superfluous intermediate variables and save resources, and the quantized coefficients are stored directly in the order of Zig-Zag scanning, and the access to memory is reduced. The quantization module supports the traditional unweighted quantization technique and the quality adjustable weighted quantization technology. The two quantization techniques reuse a scalable quantization module and save resources. In the entropy coding module, the code table is compressed according to the relation between running-level and trans_coeffcient, which reduces the complexity of searching table. In this paper, parallel pipelining is used to speed up the coding speed. In this paper, Verilog HDL language is used to complete the RTL level circuit of the AVS-S encoder, and the Synopsys VCS is used to verify the function. The AVS-S standard reference software SM2_0.4-v3 is used to build the reference model. The simulation results of VCS and the results of reference model are compared to verify the correctness of the design. Logic synthesis is carried out on the Design Compiler synthesis tool of Synopsys. The result shows that the design meets the requirement of time sequence. Finally, Formality formal verification tool is used to verify the design.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN919.81
本文编号：2141031
[Abstract]:AVS is the standard of audio and video coding and decoding of independent intellectual property rights in China. It was developed by the AVS working group on the basis of AVS, and is mainly aimed at the digital video coding and decoding standard in the field of security and surveillance. It can meet the special requirements of remote video surveillance. The proposal of this standard not only promotes the development of China's security industry, but also solves a lot of patent barriers and saves patent expenses. In this paper, the AVS-S standard is studied deeply, then the algorithms used in the transform, quantization and entropy coding modules are analyzed and optimized. Finally, the hardware design and optimization of the three modules are given. According to the characteristics of ICT transform, 1-DICT transform and 8 脳 8 transpose matrix are used to realize 2-DICT transform, the traditional butterfly algorithm is optimized, the coefficients after transformation need not be reordered, and the complexity of transformation is reduced. In the quantization module, the method of solving the weighted quantization matrix is modified to avoid the storage of superfluous intermediate variables and save resources, and the quantized coefficients are stored directly in the order of Zig-Zag scanning, and the access to memory is reduced. The quantization module supports the traditional unweighted quantization technique and the quality adjustable weighted quantization technology. The two quantization techniques reuse a scalable quantization module and save resources. In the entropy coding module, the code table is compressed according to the relation between running-level and trans_coeffcient, which reduces the complexity of searching table. In this paper, parallel pipelining is used to speed up the coding speed. In this paper, Verilog HDL language is used to complete the RTL level circuit of the AVS-S encoder, and the Synopsys VCS is used to verify the function. The AVS-S standard reference software SM2_0.4-v3 is used to build the reference model. The simulation results of VCS and the results of reference model are compared to verify the correctness of the design. Logic synthesis is carried out on the Design Compiler synthesis tool of Synopsys. The result shows that the design meets the requirement of time sequence. Finally, Formality formal verification tool is used to verify the design.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN919.81
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