高速SerDes测试设计
发布时间：2018-08-01 14:05
【摘要】：系统芯片间对数据传输速率的要求不断提高,使得串行器／解串器(Serializer and Deserializer, SerDes)技术得到了越来越多的关注。由于测试设备带宽需大于信号速率,且探针接入会对信号产生影响,因而对高速SerDes (HSS)功能芯片知识产权(IP)进行误码率与眼图的测试成为挑战。 为了对高速信号眼图测试,本论文设计了片上眼开监视器电路。相比于传统的基于模板的二维眼开监视器电路,本论文提出的设计方案无需进行初始采样时钟与眼图中心对齐的操作,测试过程设置与测试结果记录由数字控制模块完成。所提出的片上眼开监视器方案具有获得一个周期内信号眼图打开大小信息的特点。在TSMC65nm工艺下,片上眼开监视器可完成对单链路12.5Gbps信号眼图的测试,垂直偏差20mV,水平偏差4ps。 为了实现对HSS电路的误码率测试,本论文设计了片上伪随机码的产生检测电路与测试路径。为了实现对核内寄存器的读写,本论文设计了基于串口与JTAG协议的接口访问电路。在TSMC65nm工艺下,8位并行产生模块运行频率为3.2GHz,8位检测模块运行频率为1.8GHz,可应用于12.5Gbps的HSS电路中进行误码率的测试。 为了实现对仿真系统中误码率的测试,本论文提出了基于噪声模型和统计理论的系统误码率评价方法。通过矩估计量与样本容量的选取,可对仿真系统的误码率进行快速评价。基于我们提出的统计测试信噪比的方法,当样本容量选为3100,此时样本方差估计总体方差的误差在5%内的置信度达到95%,对于10-12误码率估计偏差小于一个数量级。 本论文对眼图与误码率测试HSS电路的性能是定性与定量两个方面的评价,提出电路系统与仿真系统中使用眼开监视器、内建自测试与噪声分析的测试方案,实现了对HSS功能芯片IP核的眼图与误码率的仿真测试。
[Abstract]:The requirement of data transmission rate between chips is increasing, which makes the serial / demultiplexer (Serializer and Deserializer, SerDes) technology get more and more attention. Because the bandwidth of the test equipment needs to be larger than the signal rate and the probe access will affect the signal, it is a challenge to test the bit error rate (BER) and the eye diagram of the intellectual property (IP) of the high-speed SerDes (HSS) functional chip. In order to test the high-speed signal eye chart, this paper designs the on-chip eye-open monitor circuit. Compared with the traditional two dimensional open eye monitor circuit based on template, the design of this paper does not need the operation of initial sampling clock and eye image center alignment, and the test process setting and test result recording are completed by digital control module. The proposed on-chip eye monitor scheme has the characteristics of obtaining the information of the opening size of the eye chart of the signal within a period. In the TSMC65nm process, the on-chip eye monitor can complete the test of the single link 12.5Gbps signal eye diagram, the vertical deviation is 20mV, and the horizontal deviation is 4ps. In order to test the bit error rate (BER) of HSS circuit, this paper designs the generation and detection circuit and test path of pseudorandom code on chip. In order to read and write registers in the core, the interface access circuit based on serial port and JTAG protocol is designed in this paper. The operating frequency of the 8-bit parallel generation module in TSMC65nm is 1.8 GHz, which can be used in the HSS circuit of 12.5Gbps to test the bit error rate (BER). In order to test the bit error rate (BER) in the simulation system, this paper presents a method of BER evaluation based on noise model and statistical theory. Through the selection of moment estimator and sample size, the bit error rate of the simulation system can be evaluated quickly. Based on the SNR method proposed by us, when the sample size is chosen as 3100, the confidence of the total variance of sample estimation is 95%, and the error of 10-12 BER estimation is less than one order of magnitude. In this paper, the performance of eye map and bit error rate (BER) HSS circuits is evaluated qualitatively and quantitatively. A test scheme of using eye monitor, built-in self-test and noise analysis in circuit system and simulation system is proposed. The eye diagram and bit error rate of HSS function chip IP core are simulated and tested.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN407
[Abstract]:The requirement of data transmission rate between chips is increasing, which makes the serial / demultiplexer (Serializer and Deserializer, SerDes) technology get more and more attention. Because the bandwidth of the test equipment needs to be larger than the signal rate and the probe access will affect the signal, it is a challenge to test the bit error rate (BER) and the eye diagram of the intellectual property (IP) of the high-speed SerDes (HSS) functional chip. In order to test the high-speed signal eye chart, this paper designs the on-chip eye-open monitor circuit. Compared with the traditional two dimensional open eye monitor circuit based on template, the design of this paper does not need the operation of initial sampling clock and eye image center alignment, and the test process setting and test result recording are completed by digital control module. The proposed on-chip eye monitor scheme has the characteristics of obtaining the information of the opening size of the eye chart of the signal within a period. In the TSMC65nm process, the on-chip eye monitor can complete the test of the single link 12.5Gbps signal eye diagram, the vertical deviation is 20mV, and the horizontal deviation is 4ps. In order to test the bit error rate (BER) of HSS circuit, this paper designs the generation and detection circuit and test path of pseudorandom code on chip. In order to read and write registers in the core, the interface access circuit based on serial port and JTAG protocol is designed in this paper. The operating frequency of the 8-bit parallel generation module in TSMC65nm is 1.8 GHz, which can be used in the HSS circuit of 12.5Gbps to test the bit error rate (BER). In order to test the bit error rate (BER) in the simulation system, this paper presents a method of BER evaluation based on noise model and statistical theory. Through the selection of moment estimator and sample size, the bit error rate of the simulation system can be evaluated quickly. Based on the SNR method proposed by us, when the sample size is chosen as 3100, the confidence of the total variance of sample estimation is 95%, and the error of 10-12 BER estimation is less than one order of magnitude. In this paper, the performance of eye map and bit error rate (BER) HSS circuits is evaluated qualitatively and quantitatively. A test scheme of using eye monitor, built-in self-test and noise analysis in circuit system and simulation system is proposed. The eye diagram and bit error rate of HSS function chip IP core are simulated and tested.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN407
【参考文献】
相关期刊论文 前4条
1 张俊杰;徐震柳;田进进;郑s，
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