片内云架构AVS编码I帧的优化与实现
发布时间：2018-08-03 16:54
【摘要】：随着信息技术的发展与进步,数字视频通信也成为该领域研究的热点话题之一。AVS标准是中国数字音视频编解码技术标准工作组制定的具有自主知识产权的数字音视频编码标准,性能与H.264标准相当。AVS标准已成为我国高清数字电视、网络电视、视频通信等重要音视频应用的基础标准。 AVS标准采用了一系列的先进技术,有效地提高了视频编码效率,实时编码的数据吞吐率很高。FPGA拥有丰富的寄存器资源和逻辑资源,其高性能和灵活性能够满足高速复杂电子线路设计的需求。 本研究提出一种新型架构——片内云架构,并在此架构下完成了AVS编码器Ⅰ帧的优化及实现。设计了片内只写总线(BoW)以及基于其自身特点的消息访问机制。片内只写总线网络拓扑结构简单,有利于原子构件的高度并行和流水处理,适用于处理数据量大、复杂度高的视频编码算法。将AVS算法模块封装成基于消息访问的原子构件,通过统一节点接口连接到总线上。 根据AVS编码算法的特点,本文在FPGA上设计实现了AVS编码器Ⅰ帧算法。将AVS编码Ⅰ帧的实现分为5个功能模块,将各模块封装成原子构件,包括图像采集原子构件、亮度预测变换原子构件、亮度编码原子构件和、色度预测变换原子构件和色度编码原子构件。综合考虑Ⅰ帧算法的特点和原子构件粒度的划分原则,取代传统以16×16宏块为基本单元的数据块模式,将其再一步细化为8×8块的模式。这种更精细的粒度划分有效地减少了原子构件与流程引擎间通信的时间,节省了硬件资源,提高了编码效率。 为提高数据处理的速度,实现视频的实时编码,各模块采用高度并行算法和流水线设计方法。利用该架构的本身特点,本文采用重复部署多个原子构件的方法,利用多个流程调用的并行执行方式,又进一步提高了编码效率,实现了对高分辨率图像的实时编码。通过ISE与ModelSim综合仿真,其最高时钟频率可达130MHz,可在Virtex-5平台上实现D1分辨率Ⅰ帧图像的实时编码。
[Abstract]:With the development and progress of information technology, digital video communication has become one of the hot topics in this field. AVS standard is a digital audio and video coding standard with independent intellectual property rights developed by China Digital Audio Video coding and Decoding Technical Standard working Group. The performance is equivalent to H.264 standard. AVS standard has become the basic standard of high definition digital TV, network television, video communication and other important audio and video applications. AVS standard has adopted a series of advanced technology. The efficiency of video coding is improved effectively. The data throughput of real-time coding is very high. FPGA has abundant register and logic resources, and its high performance and flexibility can meet the needs of high-speed and complex electronic circuit design. In this paper, we propose a new architecture, the in-chip cloud architecture, and optimize and implement the frame I of AVS encoder. A write-only bus (BoW) and a message access mechanism based on its own characteristics are designed. The on-chip write-only network topology is simple, which is conducive to the highly parallel and pipelined processing of atomic components. It is suitable for video coding algorithms with large data volume and high complexity. The AVS algorithm module is encapsulated as an atomic component based on message access and connected to the bus through a unified node interface. According to the characteristics of AVS coding algorithm, this paper designs and implements the frame I algorithm of AVS encoder on FPGA. The realization of AVS coding frame I is divided into five functional modules. Each module is encapsulated into atomic components, including image acquisition atomic component, brightness prediction transformation atomic component, luminance coding atomic component and, Chromaticity prediction transformation atomic component and chrominance coded atomic component. Considering the characteristics of frame I algorithm and the partition principle of atomic component granularity, this paper replaces the traditional data block mode with 16 脳 16 macroblock as the basic unit, and further refines it to 8 脳 8 block mode. The finer granularity partition reduces the communication time between the atomic component and the process engine, saves the hardware resources and improves the coding efficiency. In order to improve the speed of data processing and realize real-time video coding, each module adopts highly parallel algorithm and pipeline design method. Taking advantage of the characteristics of the architecture, this paper adopts the method of repeatedly deploying multiple atomic components, utilizes the parallel execution mode of multiple process calls, and further improves the coding efficiency and realizes the real-time coding of high-resolution images. Through the simulation of ISE and ModelSim, the highest clock frequency can be up to 130 MHz, and the D1 resolution I frame image can be encoded in real time on Virtex-5 platform.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81
本文编号：2162381
[Abstract]:With the development and progress of information technology, digital video communication has become one of the hot topics in this field. AVS standard is a digital audio and video coding standard with independent intellectual property rights developed by China Digital Audio Video coding and Decoding Technical Standard working Group. The performance is equivalent to H.264 standard. AVS standard has become the basic standard of high definition digital TV, network television, video communication and other important audio and video applications. AVS standard has adopted a series of advanced technology. The efficiency of video coding is improved effectively. The data throughput of real-time coding is very high. FPGA has abundant register and logic resources, and its high performance and flexibility can meet the needs of high-speed and complex electronic circuit design. In this paper, we propose a new architecture, the in-chip cloud architecture, and optimize and implement the frame I of AVS encoder. A write-only bus (BoW) and a message access mechanism based on its own characteristics are designed. The on-chip write-only network topology is simple, which is conducive to the highly parallel and pipelined processing of atomic components. It is suitable for video coding algorithms with large data volume and high complexity. The AVS algorithm module is encapsulated as an atomic component based on message access and connected to the bus through a unified node interface. According to the characteristics of AVS coding algorithm, this paper designs and implements the frame I algorithm of AVS encoder on FPGA. The realization of AVS coding frame I is divided into five functional modules. Each module is encapsulated into atomic components, including image acquisition atomic component, brightness prediction transformation atomic component, luminance coding atomic component and, Chromaticity prediction transformation atomic component and chrominance coded atomic component. Considering the characteristics of frame I algorithm and the partition principle of atomic component granularity, this paper replaces the traditional data block mode with 16 脳 16 macroblock as the basic unit, and further refines it to 8 脳 8 block mode. The finer granularity partition reduces the communication time between the atomic component and the process engine, saves the hardware resources and improves the coding efficiency. In order to improve the speed of data processing and realize real-time video coding, each module adopts highly parallel algorithm and pipeline design method. Taking advantage of the characteristics of the architecture, this paper adopts the method of repeatedly deploying multiple atomic components, utilizes the parallel execution mode of multiple process calls, and further improves the coding efficiency and realizes the real-time coding of high-resolution images. Through the simulation of ISE and ModelSim, the highest clock frequency can be up to 130 MHz, and the D1 resolution I frame image can be encoded in real time on Virtex-5 platform.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81
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