保护大规模集成电路知识产权的动态水印技术研究
发布时间：2018-11-15 11:39
【摘要】：随着半导体工艺的飞速发展，集成电路设计进入了片上系统（SOC: system-on-a-chip）时代。使用可复用的IP核（IP: intellectual property）技术是SOC的主流设计方法学。可复用IP核技术促进了IP核的交易，但是同时使IP核盗版、滥用等侵权现象大肆猖獗。为了保护IP核设计者和合法使用者的利益，学者提出许多保护IP核的水印技术，使得IP核水印技术受到越来越多的关注。 根据水印技术检测机制的不同，水印技术可以分为静态水印技术和动态水印技术，动态水印技术由于其易于检测的优点成为水印技术研究热点，然而动态水印技术仍然面临着水印技术的开销大，，鲁棒性差的问题。针对动态水印存在的问题，本课题主要研究FSM（finite-state machine）和DFT（design-for-testability）动态水印技术，具体包括以下内容： 本课题提出一种基于状态的FSM水印方案。水印信息被嵌入到一个特定的状态序列中，当施加一个特定的输入序列与含水印的STG，STG经历一个状态序列，根据状态的奇偶性，每个状态对应的值匹配水印信息，最后通过确定状态转移上的输出值降低水印开销。实验结果表明此方案具有较高的鲁棒性和产权可靠性，但是由于在水印嵌入过程中新加的转移数目比较多，导致水印开销比较大。为了减少新加转移的数目降低水印开销，本课题对该方案作了进一步的改进。 本课题提出一种基于BIST测试响应压缩优化算法的DFT水印技术，在实现原始优化算法的过程中发现了原算法的不足，于是本课题提出了一种改进的测试响应压缩器设计方法，在改进的算法中，对于一个固定的测试向量集，首先收集针对每一个故障的所有测试响应。在压缩的过程中，如果某一故障由于添加一个门被淹没了，就搜寻这一故障其余的测试响应不重新执行ATPG。当在响应压缩器设计过程中，添加一个基本门不得不引入冗余时，开始使用XOR门去结合输出端。实验结果表明对于比较大的电路，改进的算法和原始算法在面积开销相同的情况下，可以达到近视相同的压缩率，但是改进的算法不需要使用ATPG。本课题在上述改进的优化算法的基础上实现了一种DFT水印技术，在该水印方案中，首先选定特定输出端，当选择门结合特定的输出端时，在一个特定的输入下，使所选门的输出值恰好和水印信息匹配。分析显示该方案具有较高鲁棒性和产权可靠性，实验结果表明该水印技术对原始压缩电路的压缩率和面积影响都比较小。 为了解决动态水印技术存在的问题，本课题提出了一种新的FSM和DFT水印技术。FSM水印技术鲁棒性较高但是水印开销比较大，DFT水印技术具有高鲁棒性，低开销的特点，本课题实现了预期的目标。
[Abstract]:With the rapid development of semiconductor technology, integrated circuit design has entered the era of SOC: system-on-a-chip. Using reusable IP core (IP: intellectual property) technology is the mainstream design methodology of SOC. Reusable IP technology promotes the trade of IP nuclear, but it also makes piracy and abuse of IP nuclear rampant. In order to protect the interests of the designers and legitimate users of the IP core, many watermarking techniques are proposed to protect the IP core, which makes the IP core watermarking technology receive more and more attention. According to the different detection mechanism of watermarking technology, watermarking technology can be divided into static watermarking technology and dynamic watermarking technology. Dynamic watermarking technology has become a hot research topic because of its advantages of easy detection. However, dynamic watermarking still faces the problem of high cost and poor robustness. Aiming at the problems of dynamic watermarking, this paper mainly studies FSM (finite-state machine) and DFT (design-for-testability) dynamic watermarking technology, including the following contents: this paper proposes a state-based FSM watermarking scheme. The watermark information is embedded in a specific state sequence. When a specific input sequence is applied to the watermark, the watermark information is matched by the corresponding value of each state according to the parity of the state. Finally, the watermark overhead is reduced by determining the output value of the state transition. The experimental results show that this scheme has high robustness and property right reliability, but due to the large number of new transfers added in the process of watermark embedding, the watermark cost is relatively large. In order to reduce the number of new transfers and reduce the watermark overhead, the scheme is further improved. In this paper, a DFT watermarking technique based on BIST test response compression optimization algorithm is proposed. In the process of realizing the original optimization algorithm, the shortcomings of the original algorithm are found, so an improved design method of the test response compressor is proposed. In the improved algorithm, for a fixed set of test vectors, all the test responses for each fault are first collected. During compression, if a fault is flooded by adding a gate, search for the fault and the rest of the test response does not re-execute ATPG. When a basic gate has to be introduced redundancy in the design of the response compressor, the XOR gate is used to combine the output. Experimental results show that for larger circuits, the improved algorithm and the original algorithm can achieve the same compression ratio of myopia under the same area cost, but the improved algorithm does not need to use ATPG.. In this paper, a DFT watermarking technique is implemented on the basis of the above improved optimization algorithm. In this scheme, a specific output is first selected, and when the gate is combined with a specific output, under a specific input, The output value of the selected gate matches the watermark information. The analysis shows that the scheme has high robustness and property right reliability. The experimental results show that the watermark technology has little effect on the compression ratio and area of the original compression circuit. In order to solve the problem of dynamic watermarking technology, this paper proposes a new FSM and DFT watermarking technology. FSM watermarking technology has high robustness but high watermark overhead, and DFT watermarking technology has the characteristics of high robustness and low cost. This subject has achieved the expected goal.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP309.7
本文编号：2333205
[Abstract]:With the rapid development of semiconductor technology, integrated circuit design has entered the era of SOC: system-on-a-chip. Using reusable IP core (IP: intellectual property) technology is the mainstream design methodology of SOC. Reusable IP technology promotes the trade of IP nuclear, but it also makes piracy and abuse of IP nuclear rampant. In order to protect the interests of the designers and legitimate users of the IP core, many watermarking techniques are proposed to protect the IP core, which makes the IP core watermarking technology receive more and more attention. According to the different detection mechanism of watermarking technology, watermarking technology can be divided into static watermarking technology and dynamic watermarking technology. Dynamic watermarking technology has become a hot research topic because of its advantages of easy detection. However, dynamic watermarking still faces the problem of high cost and poor robustness. Aiming at the problems of dynamic watermarking, this paper mainly studies FSM (finite-state machine) and DFT (design-for-testability) dynamic watermarking technology, including the following contents: this paper proposes a state-based FSM watermarking scheme. The watermark information is embedded in a specific state sequence. When a specific input sequence is applied to the watermark, the watermark information is matched by the corresponding value of each state according to the parity of the state. Finally, the watermark overhead is reduced by determining the output value of the state transition. The experimental results show that this scheme has high robustness and property right reliability, but due to the large number of new transfers added in the process of watermark embedding, the watermark cost is relatively large. In order to reduce the number of new transfers and reduce the watermark overhead, the scheme is further improved. In this paper, a DFT watermarking technique based on BIST test response compression optimization algorithm is proposed. In the process of realizing the original optimization algorithm, the shortcomings of the original algorithm are found, so an improved design method of the test response compressor is proposed. In the improved algorithm, for a fixed set of test vectors, all the test responses for each fault are first collected. During compression, if a fault is flooded by adding a gate, search for the fault and the rest of the test response does not re-execute ATPG. When a basic gate has to be introduced redundancy in the design of the response compressor, the XOR gate is used to combine the output. Experimental results show that for larger circuits, the improved algorithm and the original algorithm can achieve the same compression ratio of myopia under the same area cost, but the improved algorithm does not need to use ATPG.. In this paper, a DFT watermarking technique is implemented on the basis of the above improved optimization algorithm. In this scheme, a specific output is first selected, and when the gate is combined with a specific output, under a specific input, The output value of the selected gate matches the watermark information. The analysis shows that the scheme has high robustness and property right reliability. The experimental results show that the watermark technology has little effect on the compression ratio and area of the original compression circuit. In order to solve the problem of dynamic watermarking technology, this paper proposes a new FSM and DFT watermarking technology. FSM watermarking technology has high robustness but high watermark overhead, and DFT watermarking technology has the characteristics of high robustness and low cost. This subject has achieved the expected goal.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP309.7
本文编号：2333205
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