基于AVS标准的视频解码模块的研究和实现

发布时间：2019-06-29 19:09

【摘要】：随着数字信号处理技术和计算机技术的发展进步,数字化视频的浪潮席卷全球。人们对于高清视频的应用和娱乐需求越来越大。为了解决视频的质量、存储空间及实时性等一系列问题,人们对于高效率的视频压缩标准和高性能的硬件视频解码器的研究开发力度日益加大。AVS作为具备我国自主知识产权的信源标准,兼具先进性、自主性和开放性等特点,拥有着广阔的市场前景,因此,对其硬件实现的研究有着重大的意义。本文结合AVS视频标准中阐述的算法特点,对AVS视频解码器的并行流水线进行了规划,设计了更适合于硬件实现的解码器结构。具体内容包括：(1)变长解码。在研究了AVS标准的变长解码部分后,设计并实现了桶形移位寄存器来读出相应长度的数据,运用查找表方式来实现变长码的解析。(2)残差系数处理。在反量化操作后插入缓存FIFO,实现两级流水线。把反扫描、反变换和转置操作都放在一个8x8的寄存器阵列上完成,行变换和列变换的8组数据都可以同时进行处理,无需占用存储器资源,节省了读写存储器消耗的时钟周期。(3)帧内预测和重建。分析AVS标准帧内解码的算法,提取不同模式算法的共性,合理安排片上存储器空间,在像素预测值计算时,设计一个基本运算单元完成大部分预测模式的像素预测计算,针对较为复杂的Plane模式,则专门设计Plane模式计算阵列完成其计算。(4)环路滤波。在分析了滤波算法后,对滤波边界的顺序进行适当地调整,并合理分配内部双口RAM存储器资源。将边界像素滤波操作与滤波后像素的转存操作并行进行,加快了滤波速度,节省了消耗的时钟周期。(5)帧间预测的运动矢量获取部分。针对众多的帧间预测模式和划分方式,采用命令字和标志位的方式进行归类,后续的MV计算模块根据命令字进入不同的计算分支,调用计算单元计算。对MV计算过程中数个频繁使用的复杂公式,统一设计一个计算单元,以时分复用方式实现计算。本文采用Verilog语言对各个模块进行了设计,并通过与软件rm代码比对、ModelSim软件仿真和FPGA验证的方法对AVS解码器的数个关键硬件模块进行了验证。分析表明,本设计的模块可满足AVS标清视频的实时解码要求。
[Abstract]:With the development of digital signal processing technology and computer technology, the wave of digital video swept the world. There is a growing demand for high-definition video applications and entertainment. In order to solve a series of problems, such as video quality, storage space and real-time performance, the research and development of high efficiency video compression standard and high performance hardware video decoder is increasing day by day. AVS, as a source standard with independent intellectual property rights in our country, has broad market prospects, so the research on its hardware implementation is of great significance. In this paper, according to the algorithm characteristics described in AVS video standard, the parallel pipeline of AVS video decoder is planned, and the decoder structure which is more suitable for hardware implementation is designed. The specific contents include: (1) variable length decoding. After studying the variable length decoding part of AVS standard, the bucket shift register is designed and implemented to read out the corresponding length data, and the look-up table method is used to realize the analysis of variable length code. (2) residual coefficient processing. After the inverse quantification operation, the cache FIFO, is inserted to implement the two-stage pipeline. The reverse scanning, inverse transformation and transposition operations are all completed on a register array of 8x8. Eight sets of data of row transformation and column transformation can be processed at the same time, which does not need to occupy memory resources, and saves the clock cycle consumed by read and write memory. (3) intra prediction and reconstruction. The algorithm of AVS standard intra-frame decoding is analyzed, the commonness of different mode algorithms is extracted, and the memory space on chip is arranged reasonably. When the pixel prediction value is calculated, a basic operation unit is designed to complete the pixel prediction calculation of most prediction modes, and for the more complex Plane mode, the Plane mode calculation array is specially designed to complete its calculation. (4) loop filtering. After analyzing the filtering algorithm, the order of filtering boundary is adjusted properly, and the internal dual-port RAM memory resources are allocated reasonably. The boundary pixel filtering operation is carried out in parallel with the filtered pixel transfer operation, which accelerates the filtering speed and saves the consumed clock cycle. (5) the motion vector acquisition part of inter-frame prediction. According to many inter-frame prediction modes and partition methods, the command word and flag bit are used to classify, and the subsequent MV calculation module enters different computing branches according to the command word, and calls the computing unit to calculate. For several frequently used complex formulas in the process of MV calculation, a computing unit is designed uniformly, and the calculation is realized by time division reuse (TDM). In this paper, Verilog language is used to design each module, and several key hardware modules of AVS decoder are verified by comparing with software rm code, ModelSim software simulation and FPGA verification. The analysis shows that the designed module can meet the real-time decoding requirements of AVS standard video.
【学位授予单位】：福州大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN919.81

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