基于130nm CMOS工艺UHF RFID系统中频率综合器的研究与设计

发布时间：2018-01-19 00:22

本文关键词： 射频识别技术锁相环压控振荡器电荷泵分频器　出处：《中国科学技术大学》2015年硕士论文　论文类型：学位论文

【摘要】：射频识别技术具有信息量大、无需接触即可快速识别大量物品的优点,可以极大提高物流链管理中物品信息的时效及准确度,逐渐成为学术及工业界的研究热点。另一方面,随着CMOS技术发展进入纳米时代,高度集成的片上系统成为了电路设计的主流方向,带给射频识别阅读器芯片巨大的研究及应用潜力。频率综合器为阅读器芯片提供本振信号,是决定阅读器芯片收发性能的关键部分,其设计难点在于压控振荡器和电荷泵电路的设计。本文以设计一款适用于中国大陆标准的射频识别阅读器芯片中的频率综合器为目标,提出采用双环整数型锁相环架构,并在详细分析环路各电路模块的设计方法及参数选取原则下,采用3.3V/1.8V130nm CMOS工艺实现并通过流片测试或后仿验证。高性能压控振荡器的是锁相环设计的基础,直接决定环路的带外噪声和功耗。目前主流的两种CMOS压控振荡器为环形振荡器和电感电容振荡器,本文试图以最小的功耗实现压控振荡器的最优噪声性能。在分析环振差分延时单元热噪声传递的基础上,明确给出并流片验证了延时单元中MOS管尺寸及负载类型的选取和设计原则,降低环振相位噪声。从电感选取、变容管偏置优化、电容阵列、交叉耦合管及偏置电流源管选择五个方面,提出并后仿验证了低相位噪声电感电容振荡器的优化方法。电荷泵的性能好坏影响锁相环路的带内噪声及参考杂散水平,低功耗低参考杂散是电荷泵电路设计的优化方向。本文分析了影响电荷泵参考杂散和噪声的非理想效应,给出了对应的数学模型,并据此设计了一个输出参考杂散在-88dBc以下,5位开关控制尾电流大小的电荷泵电路。最后,本文还实现了锁相环路中的数字电路模块的设计,主要指鉴频鉴相器和分频器部分。根据锁相环路中各处不同的信号工作频率,给出了锁相环中用到的三处分频器的设计方案及后仿结果。
[Abstract]:RFID technology has the advantages of large amount of information, can quickly identify a large number of items without contact, and can greatly improve the timeliness and accuracy of goods information in logistics chain management. On the other hand, with the development of CMOS technology into the nanoscale era, the highly integrated on-chip system has become the mainstream of circuit design. It brings enormous research and application potential to RFID reader chip. The frequency synthesizer provides the local oscillator signal for the reader chip, which is the key part of determining the transceiver performance of the reader chip. The design difficulty lies in the design of voltage controlled oscillator and charge pump circuit. This paper aims to design a frequency synthesizer in RFID reader chip suitable for Chinese mainland standard. A dual loop integer PLL architecture is proposed, and the design method and parameter selection principle of each circuit module of the loop are analyzed in detail. A 3.3V / 1.8V130nm CMOS process was used and the flow sheet test or post-simulation verification was carried out. The high performance VCO is the basis of PLL design, which directly determines the out-of-band noise and power consumption of the loop. At present, two kinds of CMOS VCO are ring oscillator and inductively capacitive oscillator. This paper attempts to achieve the optimal noise performance of the VCO with minimum power consumption, based on the analysis of the thermal noise transfer of the ring vibration differential delay unit. The principle of selecting and designing the size and load type of MOS tube in delay cell is clearly given. The phase noise of ring vibration is reduced from inductance selection, transformer bias optimization, capacitor array. The optimization method of low phase noise inductively capacitive oscillator is proposed and verified in the selection of cross-coupled transistors and bias current source transistors. The performance of the charge pump affects the in-band noise and the reference stray level of the PLL. Low power and low reference stray is the optimization direction of charge pump circuit design. This paper analyzes the non-ideal effects of the charge pump reference stray and noise, and gives the corresponding mathematical model. Based on this, a charge pump circuit with output reference stray below -88dBc is designed. Finally, the design of the digital circuit module in the PLL is realized, which mainly refers to the frequency discriminator and the frequency divider. According to the different signal operating frequency in the PLL. The design scheme and post-simulation results of three frequency dividers used in PLL are given.
【学位授予单位】：中国科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74;TP391.44

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