智能制造车间级网络构建及其安全设计

发布时间：2018-05-04 23:44

本文选题：智能制造 + 网络安全　；参考：《西华大学》2017年硕士论文

【摘要】：《中国制造2025》和《智能制造发展规划(2016-2020)》的相继发布,加快了我国智能制造的规划和布局,以全力抢占先进制造业发展的制高点。随着信息化和工业化的不断深度融合,工业互联网开放程度越来越高,这也向网络信息安全提出了严峻的挑战,如何解决智能制造中网络信息安全问题变得迫在眉睫。本论文针对智能制造车间级网络,分析并设计了网络安全方案和数据加密方式。在此基础上,首先完成了系统硬件平台的电路设计。电路设计包括系统电源ADP5050、FPGA参考时钟和参考电源、JTAG配置、DDR3存储K4B2G1646C、千兆以太网KSZ9031MNX、以太网连接器RJ45等模块。在网络安全和密码及编码学的研究基础上,采用自顶而下的设计思想完成了系统的软件设计。软件设计分为两部分,一部分接口FPGA,另一部分为算法FPGA。接口FPGA软件设计主要包含千兆以太网PHY配置,UDP协议、IP协议、ARP协议、DDR3的转换控制及UniPHY IP配置、数据收发等模块;算法FPGA软件设计主要包含数据的输入寄存和校验、AES密钥扩展、AES加解及解密算法、SM4密钥扩展、SM4加解及解密算法和SM3算法等模块。在设计过程中分析了FPGA的片上资源及Verilog编码效率。完成了系统仿真。利用Modsim完成了各子模块和系统整体的RTL级仿真,并对仿真结果进行了分析和判断。最后设计了系统的测试方案,并完成了系统的子模块和整体测试。子模块测试主要利用QuartusII的Signal Tap II嵌入式逻辑分析仪获取FPGA的片内的待测信号,而整体测试主要利用Wireshark和网络调试助手来获取UDP加密和解密包。子模块和整体测试均包含了功能、性能和稳定性三个方面,并对测试结果做出了分析和判断。实验结果表明,本文设计的车间级网络方案实现了网络数据的机密性和认证功能,为智能制造网络信息安全研究提供了良好的基础研究。
[Abstract]:The release of "made in China 2025" and "Intelligent Manufacturing Development Plan 2016-2020" one after another has accelerated the planning and layout of intelligent manufacturing in China, in order to seize the commanding point of the development of advanced manufacturing industry. With the continuous integration of information and industrialization, the opening degree of the industrial Internet is becoming more and more high, which also poses a severe challenge to network information security. How to solve the problem of network information security in intelligent manufacturing becomes urgent. In this paper, the network security scheme and data encryption method are analyzed and designed for intelligent manufacturing shop level network. On this basis, the circuit design of the system hardware platform is first completed. The circuit design includes ADP5050 FPGA reference clock and JTAG configuration DDR3 storage K4B2G1646C, Gigabit Ethernet KSZ9031MNXand Ethernet connector RJ45. Based on the research of network security and cryptography and coding, the software design of the system is completed by using the top-down design idea. The software design is divided into two parts, one is the interface FPGA, the other is the algorithm FPGA. The design of interface FPGA software mainly includes the conversion control, UniPHY IP configuration, data transceiver and so on of Gigabit Ethernet PHY configuration, IP protocol, IP protocol and DDR3. The algorithm FPGA software design mainly includes the data input register and the verification AES key extension AES encryption and decryption algorithm SM4 key extension SM4 encryption and decryption algorithm and SM3 algorithm and so on. In the process of design, the on-chip resource and Verilog coding efficiency of FPGA are analyzed. The system simulation is completed. The RTL level simulation of each sub-module and the whole system is completed by using Modsim, and the simulation results are analyzed and judged. Finally, the test scheme of the system is designed, and the sub-module and the whole test of the system are completed. The sub-module test mainly uses QuartusII's Signal Tap II embedded logic analyzer to obtain the on-chip test signal of FPGA, while the whole test mainly uses Wireshark and network debugging assistant to obtain UDP encryption and decryption packet. The sub-module and the whole test include three aspects: function, performance and stability, and the test results are analyzed and judged. The experimental results show that the network scheme designed in this paper realizes the confidentiality and authentication of network data, and provides a good foundation for the research of intelligent manufacturing network information security.
【学位授予单位】：西华大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TH18

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