基于65nm CMOS的快速响应LDO设计

发布时间：2018-06-26 01:36

本文选题：电源管理 + 低压差线性稳压器　；参考：《西安邮电大学》2017年硕士论文

【摘要】：集成电路设计水平的进步推动了无线通信、移动互联网以及物联网等产业飞速发展,需要片上系统集成越来越多的模块和功能,这也使系统芯片内部的电源管理技术变得尤为重要。低压差线性稳压器(Low-Dropout Regulator,LDO)是电源管理电路中常用的一种直流稳压器,具有输出稳定、易集成和低噪声等优点。传统结构LDO需要在输出端外接分立电容来保证LDO的稳定性和瞬态特性,不利于系统芯片集成度的提高。无片外电容LDO(Capacitor-less LDO,CL-LDO)避免了外接分立器件,但其稳定性和瞬态响应的优化成为了设计难点。本文面向"5G高速数据转换接口"芯片,拟设计一种无片外电容的快速响应LDO,以满足芯片内部电源管理模块的要求。本文CL-LDO主要由电压基准电路、误差放大器、反馈网络以及瞬态响应优化电路四个模块组成,重点针对CL-LDO的稳定性差、响应速度慢的缺点进行改进,具体方案包括:1.为了提高CL-LDO的瞬态响应,本文提出了一种新型的CL-LDO瞬态响应优化电路。通过引入辅助的快速检测和调整回路,根据检测到的LDO输出上冲或下冲电压,自适应地动态调整输出驱动电流的大小,进而提高对负载的响应速度,并且能够减小LDO的输出过冲和下冲电压。2.在误差放大器的设计上,本文采用两级运放结构来实现基准电压和反馈电压的比较和放大。相比其它类型的结构,两级运放在满足电压增益要求的前提下更容易提供合适的输出摆幅。在环路稳定性方面,本文采用带调零电阻的密勒补偿来保证整个环路的相位裕度,片内补偿电容为5 pF。3.本文采用电流求和的温度补偿方式设计了0.8 V电压基准电路,能够在较宽的温度范围内为LDO提供稳定的参考电压。在版图布局方面,运放输入对管采取对称布局、伪管保护的方式进行设计,电阻反馈网络采取分段组合、对称布局以及伪电阻保护等方法进行设计,以满足匹配性要求。整个电路基于65nm CMOS工艺设计实现,采用Cadence工具进行电路设计、版图设计和仿真。本文设计的CL-LDO有源面积为160μm×130μm,输入电压为1.5～2.5 V,输出电压为1.2 V,最大输出驱动电流为10 mA,最低压差电压为300 mV。在输入电压为2.5 V的空载条件下,静态电流为87μA。通过采取本文提出的瞬态响应优化电路,当负载电流以1μs的上升和下降时间在100μA～10mA之间转换时,本文CL-LDO输出过冲电压和下冲电压分别从原来的68 mV和94 mV减小到22 mV左右,输出电压在1.04 μs时间内即可稳定到0.5%的精度范围。
[Abstract]:The development of integrated circuit design level has promoted the rapid development of wireless communication, mobile Internet and Internet of things, which requires more and more modules and functions of on-chip system integration. This also makes the system chip internal power management technology becomes particularly important. Low-Dropout regulator (LDO) is a kind of DC voltage regulator commonly used in power management circuits. It has the advantages of stable output, easy integration and low noise. The conventional LDO requires a discrete capacitor outside the output to ensure the stability and transient characteristics of the LDO, which is not conducive to the improvement of the integrated level of the system chip. Non-chip capacitive LDO (Capacitor-less LDO CL-LDO) avoids external discrete devices, but the optimization of its stability and transient response becomes difficult. In this paper, a fast response LDO without off-chip capacitance is designed for the "5G high-speed data conversion interface" chip to meet the requirements of the internal power management module of the chip. In this paper, CL-LDO is mainly composed of four modules: voltage reference circuit, error amplifier, feedback network and transient response optimization circuit. In order to improve the transient response of CL-LDO, a novel CL-LDO transient response optimization circuit is proposed in this paper. By introducing the auxiliary fast detection and adjusting loop, according to the detected LDO output upburst or downburst voltage, the output driving current can be adjusted adaptively and the response speed to the load can be improved. And it can reduce the output overshoot and undershoot voltage of LDO. In the design of error amplifier, a two-stage operational amplifier structure is used to compare and amplify the reference voltage and feedback voltage. Compared with other types of structures, two-stage operation is easier to provide a suitable output swing on the premise of satisfying the voltage gain requirements. In the aspect of loop stability, Miller compensation with zero adjustable resistance is used to ensure the phase margin of the whole loop. The compensation capacitance is 5 pF.3. In this paper, a 0.8 V voltage reference circuit is designed by means of temperature compensation of current summation, which can provide a stable reference voltage for LDO in a wide temperature range. In the layout aspect, the operational amplifier input adopts the symmetrical layout, the pseudotube protection is designed, the resistive feedback network is designed by the piecewise combination, the symmetrical layout and the pseudoresistor protection, so as to meet the matching requirements. The whole circuit is implemented on the basis of 65nm CMOS process design, and the circuit design, layout design and simulation are carried out with Cadence tool. The designed CL-LDO active area is 160 渭 m 脳 130 渭 m, the input voltage is 1.5 V / 2.5 V, the output voltage is 1.2 V, the maximum output driving current is 10 Ma, and the lowest voltage difference voltage is 300 MV. When the input voltage is 2.5 V, the static current is 87 渭 A. By adopting the transient response optimization circuit proposed in this paper, when the load current is converted between 100 渭 A~10mA and 1 渭 s, the output overshoot voltage and downshoot voltage of CL-LDO are reduced from 68mV and 94mV to about 22mV, respectively. The output voltage can be stabilized to a precision range of 0.5% in 1.04 渭 s.
【学位授予单位】：西安邮电大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TM44

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