具有数字校准功能的双相并联Buck型DC-DC芯片的设计

发布时间：2018-01-11 07:28

本文关键词：具有数字校准功能的双相并联Buck型DC-DC芯片的设计　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

更多相关文章： 降压型 数字校准 锁相环 双相并联

【摘要】：随着集成电路技术的快速发展以及便携式电子设备的广泛应用,对电子市场中的电源管理设备的要求也越来越高。其中开关电源以外围器件少、效率高和体积小的优点在电源管理类芯片中得到青睐,而传统的开关电源依然存在着带载能力不足、输出电压不精确、纹波大等缺陷,因此研究能满足大负载、低功耗、小纹波和高准确度应用要求的电源管理芯片意义重大。本文基于降压型DC-DC转换器基本工作原理,提出了具有数字校准功能的双相并联Buck型DC-DC芯片的设计与实现。该芯片采用连续工作模式和峰值电流模式控制的脉冲宽度调制方式,具有对大负载的快速瞬态响应能力、片外易补偿、输出电压可校准等特点。论文介绍了Buck型DC-DC的基本工作原理及各种工作模式下的稳态分析,在此基础上引出了外部数字校准功能,并对其进行了详细的理论分析。芯片已通过仿真验证可以满足对输出电压进行±15%幅度内的校正,减小了由内部基准电压不准确或者输出线损导致的输出误差,得到精确的输出电压。同时论文就双相并联大负载的应用详细分析了可用于外同步的锁相环技术和双相并联技术,锁相环技术使得内部时钟可与外部时钟同步,实现100kHz~1MHz的频率锁定范围,满足双相并联应用中两个芯片的时钟同步,相位相差180度。通过多主控器模式和单主控器模式的均流技术,可以实现两个芯片并联应用时,电感电流纹波的抵消和小纹波电压的输出,解决了小输入输出电容大负载12A输出和稳定性的折中。论文首先对各种类型的开关电源作了简要的概述,并针对降压型DC-DC转换器的拓扑结构和工作原理进行了详细的分析,同时对降压型DC-DC转换器的断续导通和连续导通两种工作模式下的稳态特性以及系统的调制方式进行了比对和详细描述;然后重点介绍了数字校准功能、锁相环技术以及双相并联技术;最后对芯片的整体功能、外围器件的选择和稳定性进行了分析,并以带隙基准电压模块、电流采样模块和脉冲宽度调制比较器模块为例简要分析了芯片子模块的设计过程及原理,同时简单介绍了芯片在版图设计过程中需要注意的几个方面。本文所提出的具有数字校准功能的双相并联Buck型DC-DC芯片,目前已基于0.35μm BCD工艺,在Cadence软件平台上,利用Spectre仿真环境在不同的工艺角和不同的环境温度下对单芯片的子模块和整体、数字校准功能以及双相并联大负载应用完成了仿真验证,仿真结果证明该芯片可以实现对输出电压的数字校准和双相并联大负载的应用。
[Abstract]:With the rapid development of integrated circuit technology and the wide application of portable electronic equipment, the requirement of power management equipment in electronic market is more and more high. The advantages of high efficiency and small size are favored in the power management chip, but the traditional switching power supply still has shortcomings such as insufficient load capacity, inaccurate output voltage, large ripple, so the research can meet the heavy load. Low power consumption, small ripple and high accuracy requirements of the power management chip is of great significance. This paper is based on the basic principle of the step-down DC-DC converter. This paper presents the design and implementation of a dual-phase parallel Buck DC-DC chip with digital calibration function, which adopts the pulse width modulation mode controlled by continuous operation mode and peak current mode. It has the characteristics of fast transient response to large load, easy compensation out of chip and calibrating output voltage. This paper introduces the basic working principle of Buck type DC-DC and the steady state analysis under various working modes. On this basis, the external digital calibration function is introduced, and the detailed theoretical analysis is given. The chip has been verified by simulation to achieve 卤15% amplitude correction of the output voltage. The output error caused by the inaccuracy of the internal reference voltage or the output line loss is reduced. At the same time, the paper analyzes in detail the phase-locked loop technology and the two-phase parallel connection technology, which can synchronize the internal clock and the external clock. The frequency locking range of 100kHz 1MHz is realized, and the clock synchronization between the two chips is satisfied, and the phase difference is 180 degrees. The current sharing technology of multi-master controller mode and single master controller mode is adopted. When two chips are applied in parallel, the current ripple cancellation and the output of small ripple voltage can be realized. The tradeoff between 12A output and stability of small input output capacitor with large load is solved. Firstly, various types of switching power supply are briefly summarized in this paper. The topology and working principle of the reduced voltage DC-DC converter are analyzed in detail. At the same time, the steady-state characteristic and modulation mode of DC-DC converter are compared and described in detail. Then the digital calibration function, phase-locked loop technology and two-phase parallel technology are introduced. Finally, the overall function of the chip, the selection and stability of peripheral devices are analyzed, and the bandgap voltage module is used as reference. The current sampling module and the pulse width modulation comparator module are used as examples to analyze the design process and principle of the chip sub-module. At the same time, this paper briefly introduces several aspects that should be paid attention to in the process of layout design. A dual-phase parallel Buck DC-DC chip with the function of digital calibration is proposed in this paper. At present, based on 0.35 渭 m BCD process, it is on the Cadence software platform. The Spectre simulation environment is used to verify the sub-module and the whole module of the single chip, the digital calibration function and the dual-phase parallel large load application under different process angles and different ambient temperature. The simulation results show that the chip can realize the digital calibration of output voltage and the application of double phase parallel large load.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TM46

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