HVDC引发的次同步振荡原因分析及综合阻尼抑制策略研究

发布时间：2018-01-28 17:41

本文关键词： 高压直流输电次同步振荡附加次同步振荡阻尼控制器附加励磁阻尼控制器静态无功发生器　出处：《华北电力大学(北京)》2014年硕士论文　论文类型：学位论文

【摘要】：在我国能源与电力负荷分布极不均匀与电力系统互联趋势的大背景下,高压直流输电技术被广泛应用于电力系统中,由直流输电引起的次同步振荡问题也越来越引起注意,因此,为了保证汽轮发电机组安全运行,对高压直流输电(HVDC)引起的次同步振荡(SSO)问题抑制措施的研究具有相当重要的意义。论文以由HVDC引发SSO抑制措施为研究重点,首先对网侧抑制措施宽频带附加次同步阻尼控制器(SSDC)的抑制机理和设计思路进行了论述；在建立SSDC控制回路的基础上,对SSDC产生电气阻尼表达式进行了理论推导,定量揭示了SSDC的抑制能力,并给出了SSDC抑制效果影响因素与抑制能力的表达式；最后针对典型HVDC与串补外送系统在HVDC整流侧设计SSDC,并通过时域仿真对SSDC对SSO抑制的有效性及上述理论分析的正确性进行了验证。对厂侧抑制措施附加励磁阻尼控制器(SEDC)与静态无功发生器(SVG)的抑制机理和设计思路进行了论述,着重对SVG上层控制策略进行了设计；在对两种抑制措施控制回路分析的基础上,分别对SEDC与SVG产生电气阻尼表达式进行了理论推导,定量揭示两种措施的抑制能力,并给出了两种措施抑制效果影响因素抑制能力的表达式；最后针对典型HVDC与串补外送系统在厂侧设计SEDC与SVG,并通过时域仿真对SEDC、SVG对SSO抑制的有效性及上述理论分析的正确性进行了验证。在对典型系统抑制措施分析建模上,针对实际情况中可能出现的各抑制措施抑制能力不足的现象,提出了在网侧采取SSDC与在厂侧采取SEDC与SVG共同协调抑制由HVDC引起的SSO的策略；从原理上分析了SEDC与SVG在抑制SSO时的能够进行共同协调抑制的机理,并通过对电气阻尼进行理论推导提出了各抑制措施在抑制能力上的等价指标,最后通过时域仿真验证了协调抑制与抑制能力等价的正确性。
[Abstract]:Under the background of uneven distribution of energy and power load and interconnection of power system, HVDC technology is widely used in power system. The problem of subsynchronous oscillation caused by DC transmission has been paid more and more attention, therefore, in order to ensure the safe operation of turbogenerator. It is of great significance to study the suppression measures of subsynchronous oscillation (SSOs) caused by HVDC. The emphasis of this paper is on SSO suppression caused by HVDC. Firstly, the suppression mechanism and design idea of broadband additional sub-synchronous damping controller (SSDC) are discussed. Based on the establishment of SSDC control loop, the expression of electrical damping produced by SSDC is derived theoretically, and the restraining ability of SSDC is revealed quantitatively. The factors influencing the inhibition effect of SSDC and the expression of its inhibition ability are also given. Finally, SSDC is designed on the HVDC rectifier side for typical HVDC and serial compensation outputting system. The validity of SSDC to SSO suppression and the correctness of the above theoretical analysis are verified by time-domain simulation. The additional excitation damping controller (SEDC) and static reactive power generator (SvG) are applied to the factory side suppression measures. The inhibition mechanism and design idea of SVG are discussed. The upper control strategy of SVG is mainly designed. Based on the analysis of the control loops of the two kinds of suppression measures, the expressions of electrical damping produced by SEDC and SVG are deduced theoretically, and the inhibition ability of the two measures is revealed quantitatively. The expression of the inhibition ability of two kinds of measures is given. Finally, SEDC and SVG are designed on the factory side for typical HVDC and serial compensation system, and SEDC is simulated in time domain. SVG verifies the validity of SSO suppression and the correctness of the above theoretical analysis. In view of the actual situation may occur in the inhibition of the various measures of the phenomenon of inadequate capacity. The strategy of adopting SSDC on the network side and adopting SEDC and SVG on the factory side to coordinate the inhibition of SSO caused by HVDC is put forward. The mechanism that SEDC and SVG can coordinate the inhibition of SSO is analyzed in principle. Through the theoretical derivation of the electrical damping, the equivalent indexes of the inhibition ability of the various suppression measures are put forward. Finally, the correctness of the equivalence between the coordinated suppression and the suppression ability is verified by the time domain simulation.
【学位授予单位】：华北电力大学(北京)
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM712

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