实时信号分析仪中PXIE高速接口的设计与实现

发布时间：2018-03-08 17:53

  本文选题：实时信号分析仪　切入点：PXI　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：实时信号分析仪是无线通信、航空、导航等领域中广泛使用的一种测试仪器。数字化、宽频带、高分辨率已成为实时信号分析仪的发展趋势,这要求数据总线具备高传输带宽,高稳定性和可靠性。PXIE(面向仪器的PCIE总线扩展)是现在主流的仪器总线技术,PCI Express v2.0达到5.0Gb/s的传输速率,PCIE差分串行传输和纠错机制有力的保证了数据传输的质量。本文采用PXIE来实现实时信号分析仪中大量数据的高速稳健传输。要完成设计首先需要对PXIE硬件规范和PCIE传输协议作深入的理解;再通过需求分析,给出PXIE高速接口的总体方案设计,并结合PXIE总线的实现方式,设计以FPGA为主体器件的详细硬件实现方案,以及为实现数据高速传输,确立了PXIE传输协议、DMA控制器和高速缓存的逻辑设计方案;然后根据硬件实现方案,使用Cadence软件作了详细电路图设计,设计的主要考虑因素是系统性能、功耗和集成度;最后根据逻辑设计方案,使用ISE14.2综合开发平台完成PXIE传输协议、DMA控制器和高速缓存的各模块详细逻辑设计和RTL级代码编写。其中DMA控制器和高速缓存的逻辑设计是本文重中之重。本文实现了PIO、DMA和中断这三种数据传输方式。使用FIFO、RAM和DDR3这三种方式来完成不同类数据的缓存。在板卡硬件调试完成后,搭建FPGA逻辑调试平台,对逻辑设计部分使用Xilinx ISE14.2综合开发平台自带的Chipscope软件进行在线调试验证,主要包括高速接口的PIO功能、DMA功能、中断功能。DMA读传输速率达到5.78Gb/s,DMA写的传输速率达到13.33 Gb/s,中断信号工作正常,调试验证结果与设计指标相符,达到预期性能,表明方案设计、硬件电路和FPGA逻辑的正确性。本文高速接口硬件和逻辑设计已成功应用于信号分析仪中。
[Abstract]:Real-time signal analyzer is a kind of testing instrument widely used in wireless communication, aviation, navigation and other fields. Digitization, wide band and high resolution have become the development trend of real-time signal analyzer, which requires the data bus to have high transmission bandwidth. High stability and reliability. PXIE. is the mainstream instrument bus technology. PCI Express v2.0 achieves the transmission rate of 5.0 GB / s. PCIE differential serial transmission and error correction mechanism can guarantee the quality of data transmission. In this paper, PXIE is used to realize the high speed and robust transmission of a large amount of data in the real-time signal analyzer. In order to complete the design, it is necessary to have a deep understanding of the PXIE hardware specification and the PCIE transmission protocol. Then through the requirement analysis, the overall scheme design of PXIE high-speed interface is given, and combining with the realization mode of PXIE bus, the detailed hardware implementation scheme with FPGA as the main device is designed, and in order to realize the high speed data transmission, The logic design scheme of PXIE transmission protocol and cache is established, and then the detailed circuit diagram is designed by using Cadence software according to the hardware implementation scheme. The main factors of the design are system performance, power consumption and integration. Finally, according to the logical design scheme, The ISE14.2 integrated development platform is used to complete the detailed logic design of each module of PXIE transport protocol controller and cache and the coding of RTL level code. Among them, the logical design of DMA controller and cache is the most important part of this paper. There are three kinds of data transmission modes: PIOODMA and interrupt. We use FIFO RAM and DDR3 to cache different kinds of data. After the hardware debugging of the board is finished, The FPGA logic debugging platform is built, and the online debugging and verification of the Chipscope software which is included in the Xilinx ISE14.2 integrated development platform is carried out in the logic design part, which mainly includes the PIO function of the high-speed interface. The interrupt function .DMA read transmission rate reached 5.78 GB / s / s, the transmission rate reached 13.33 GB / s, the interrupt signal worked normally, the debugging and verification results were in line with the design index, and the expected performance was achieved, which indicated that the scheme was designed. The hardware and logic design of high speed interface in this paper has been successfully applied to signal analyzer.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM935
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本文编号：1584937