一种高效率降压型DC-DC变换器的设计

发布时间：2018-07-17 00:04

【摘要】：随着近些年来便携式电子产品的爆发式增长,与其直接相关的电源管理芯片的市场也得到了高速成长,对电源管理芯片的要求也越来越高,包括更高的效率、更低的功耗及更高的可靠性等。本文正是针对目前电源管理芯片技术发展的要求,分析并设计了一款高效率同步整流降压型DC-DC变换器。本文首先介绍了降压型DC-DC的拓扑结构和基本工作原理,详细阐述了三种经典的DC-DC变换器的控制模式的优缺点。为提高芯片效率,引入同步整流技术,介绍了同步整流技术的原理及存在的问题。又进一步详细分析DC-DC变换器的损耗产生原因,为减小损耗提供理论基础。最后根据芯片的参数指标要求和基础理论,提出了系统的整体设计方案,并建立数学模型,利用Matlab工具进行仿真,验证了方案的可行性。根据电路的总体架构来进一步设计可实现的电路,本文重点介绍了该系统中的重点电路模块,包括带隙基准源、误差放大器和保护电路等,并利用Hspice工具对其进行了仿真验证。完成了模块设计后,将整个电路进行联合仿真。芯片实现采用华润上华0.5微米BCD工艺,利用Hspice进行仿真。仿真结果表明该芯片能稳定输出0.8V到10V的连续电压,效率可高达95%,输出纹波低于输出电压的1%,具有良好的线性调整率和负载调整率,达到设计指标要求。
[Abstract]:With the explosive growth of portable electronic products in recent years, the market of power management chips directly related to them has also been growing at a high speed, and the demand for power management chips has become increasingly high, including higher efficiency. Lower power consumption and higher reliability. This paper analyzes and designs a high efficiency synchronous rectifier and step-down DC-DC converter according to the requirement of the development of power management chip technology. In this paper, the topology and basic working principle of DC-DC are introduced, and the merits and demerits of three classical DC-DC converters are described in detail. In order to improve chip efficiency, the principle and problems of synchronous rectification technology are introduced. Furthermore, the cause of loss in DC-DC converter is analyzed in detail, which provides a theoretical basis for reducing the loss. Finally, according to the requirements of the chip parameters and the basic theory, the overall design scheme of the system is put forward, and the mathematical model is established. The feasibility of the scheme is verified by using Matlab tools. According to the overall structure of the circuit, the paper introduces the key circuit modules of the system, including bandgap reference source, error amplifier and protection circuit, and simulates the circuit by HSPICE. After completing the module design, the whole circuit is simulated jointly. The chip is realized by China Resources (China Resources) 0.5 micron BCD process and simulated by HSPICE. The simulation results show that the chip can stably output the continuous voltage from 0.8 V to 10 V, the efficiency can reach 95%, the output ripple is lower than the output voltage, and the output ripple is lower than the output voltage. The chip has good linear adjustment rate and load adjustment rate, and meets the design requirements.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM46

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