双通道数字化仪中频及基带信号处理模块的设计与实现
发布时间：2018-09-01 11:39
【摘要】：数字化仪是模拟信号与数字信号对接的重要手段,并同时具有数字信号处理能力。具备双通道高速信号采集和处理功能的数字化仪通过与接收机模块和工控机模块的互联,可以完成示波器、频谱分析仪、无线通信分析仪、无线电测向仪等系统。高速的双通道数字化仪可以同时对两个模拟目标进行分析,在实时频谱分析仪中即可以完成所覆盖频率范围内任意两个频点的实时分析,也可以分别对基带信号的I、Q两路同步采集完成基带I/Q调制分析;在无线电测向系统中可以一路采集参考通道,另一路轮流采集各接收通道,完成测向定位的功能。本文主要基于PXI总线双通道数字化仪项目运用背景,提出了PXI总线双通道数字化仪的设计方案,重点对双通道数字化仪中频及基带信号处理模块关键技术进行了大量研究并实现了具体电路。其中双路ADC与FPGA之间交互数据位宽和时钟频率都很高(采用DDR传输模式),为了保证每次完成布局布线数据与时钟(DCO)不因在FPGA内部产生相对延迟而造成读数错误,本文设计并实现了一种能完成数据时钟自动同步的DLL电路,提高了开发效率;而多档位数字下变频单元提出了一种高效的分数倍抽取滤波器组架构(CIC抽取+CIC补偿+CIC插值),核心的分数倍抽取滤波电路都采用高效结构实现,节省资源的同时使得双通道数字化仪的RTBW(实时分辨率带宽)达到了42个,从而满足了更灵活的分析需求;针对为了节省或高效利用片内资源而减小处理位宽所引起的动态范围损失的问题,本文提出了一种动态范围补偿的高效增益控制电路结构,并避免了除法运算操作,在减小位宽和资源消耗的同时也保证了动态范围;为了满足用户对I/Q基带信号调制分析的需求,本文充分利用双通道数字化仪可以完成双路信号并行采集的特点,提出了一种能对0~51.2Msps范围内任意码率的QPSK和4~256QAM基带信号完成调制分析的硬件处理架构。本论文所论述的双通道数字化仪中频及基带信号处理模块各个功能单元能够正常可靠工作,达到预定指标和工程运用要求,在大量实践与测试中性能稳定,该数字化仪可运用于常见的通信测试系统或仪器。
[Abstract]:Digitizer is an important means of docking analog signal and digital signal, and has the ability of digital signal processing at the same time. The digital instrument with dual channel high-speed signal acquisition and processing can complete the oscilloscope, spectrum analyzer, wireless communication analyzer, radio direction finder and so on through the interconnection with receiver module and industrial computer module. High-speed dual-channel digitizer can analyze two analog targets at the same time. In the real-time spectrum analyzer, the real-time analysis of any two frequency points in the frequency range can be completed. In the radio direction-finding system, reference channels can be collected one way, and the receiving channels can be collected in turn on the other side to complete the function of direction finding and positioning. Based on the application background of PXI bus dual-channel digitizer, this paper puts forward the design scheme of PXI bus dual-channel digitizer. The key technology of if and baseband signal processing module of dual channel digitizer is studied and the specific circuit is realized. The interactive data bit width and clock frequency between dual ADC and FPGA are both very high (using DDR transmission mode). In order to ensure that each completion of layout routing data and clock (DCO) does not cause reading errors due to the relative delay within FPGA. In this paper, we design and implement a kind of DLL circuit which can realize the automatic synchronization of data clock, and improve the efficiency of development. A high efficient fractional decimation filter bank architecture (CIC decimation CIC compensated CIC interpolation) is proposed by multi-shift digital down-conversion unit. The core fractional decimation filter circuits are all implemented with efficient structure. At the same time, the RTBW (real-time resolution bandwidth) of the dual-channel digitizer is 42, which meets the more flexible analysis requirements. In order to reduce the dynamic range loss caused by processing bit width in order to save or efficiently utilize in-chip resources, this paper presents an efficient gain control circuit structure with dynamic range compensation, and avoids division operation. In order to meet the needs of the user for I / Q baseband signal modulation analysis, this paper makes full use of the dual channel digitizer to complete the dual signal parallel acquisition. This paper presents a hardware processing architecture that can modulate and analyze QPSK and 4~256QAM baseband signals at any bit rate in the 0~51.2Msps range. In this paper, if and baseband signal processing modules of the dual-channel digitizer can work normally and reliably, which can meet the requirements of predefined targets and engineering applications, and have a stable performance in a large number of practices and tests. The digitizer can be used in common communication test systems or instruments.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM935
本文编号：2217087
[Abstract]:Digitizer is an important means of docking analog signal and digital signal, and has the ability of digital signal processing at the same time. The digital instrument with dual channel high-speed signal acquisition and processing can complete the oscilloscope, spectrum analyzer, wireless communication analyzer, radio direction finder and so on through the interconnection with receiver module and industrial computer module. High-speed dual-channel digitizer can analyze two analog targets at the same time. In the real-time spectrum analyzer, the real-time analysis of any two frequency points in the frequency range can be completed. In the radio direction-finding system, reference channels can be collected one way, and the receiving channels can be collected in turn on the other side to complete the function of direction finding and positioning. Based on the application background of PXI bus dual-channel digitizer, this paper puts forward the design scheme of PXI bus dual-channel digitizer. The key technology of if and baseband signal processing module of dual channel digitizer is studied and the specific circuit is realized. The interactive data bit width and clock frequency between dual ADC and FPGA are both very high (using DDR transmission mode). In order to ensure that each completion of layout routing data and clock (DCO) does not cause reading errors due to the relative delay within FPGA. In this paper, we design and implement a kind of DLL circuit which can realize the automatic synchronization of data clock, and improve the efficiency of development. A high efficient fractional decimation filter bank architecture (CIC decimation CIC compensated CIC interpolation) is proposed by multi-shift digital down-conversion unit. The core fractional decimation filter circuits are all implemented with efficient structure. At the same time, the RTBW (real-time resolution bandwidth) of the dual-channel digitizer is 42, which meets the more flexible analysis requirements. In order to reduce the dynamic range loss caused by processing bit width in order to save or efficiently utilize in-chip resources, this paper presents an efficient gain control circuit structure with dynamic range compensation, and avoids division operation. In order to meet the needs of the user for I / Q baseband signal modulation analysis, this paper makes full use of the dual channel digitizer to complete the dual signal parallel acquisition. This paper presents a hardware processing architecture that can modulate and analyze QPSK and 4~256QAM baseband signals at any bit rate in the 0~51.2Msps range. In this paper, if and baseband signal processing modules of the dual-channel digitizer can work normally and reliably, which can meet the requirements of predefined targets and engineering applications, and have a stable performance in a large number of practices and tests. The digitizer can be used in common communication test systems or instruments.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM935
【参考文献】
相关硕士学位论文 前1条
1 宋丹;数字下变频器中自动增益控制电路的设计与实现[D];电子科技大学;2006年
，本文编号：2217087
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