RS译码算法的研究和FPGA设计

发布时间：2018-01-04 15:09

本文关键词：RS译码算法的研究和FPGA设计　出处：《东南大学》2015年硕士论文　论文类型：学位论文

更多相关文章： RS码 BM算法 FPGA JPWL

【摘要】：Reed-Solomon码(RS码)是一种性能优异,特别适合于纠正连续突发错误的信道编码方式,在诸如DVD、CD、数字电视、数字图像、数字音频、深空探测、DVB、数字通信系统、DAB等工程领域中都得到了广泛应用。JPEG2000无线传输标准(JPWL)中也规定了对图像数据帧的主头部和块头部以及其他重要信息通过RS码进行保护,所以研究RS解码的硬件实现就很有意义。由于RS解码最普遍采用的算法是BM算法,所以本文首先详细介绍了RS解码的BM算法及其各个改进版本,然后分析了BM算法的电路框图和硬件复杂度。针对RS(255,239)码型,对关键路径较短、电路结构规则的riBM算法用C++进行了软件仿真,验证了算法的正确性。本文还研究了基于伴随值矩阵的性质的步进解码算法及其各个改进版本,并设计了步进解码算法中最关键的行列式计算电路。本文利用状态转移图、算法依赖图等数字电路设计方法设计了各类有限域运算部件、RS编码器、基于riBM算法的RS解码器以及可能用于RS解码器的各个模块。所设计的RS解码器中的各个模块之间以流水线方式工作,码字可以连续输入解码器进行解码。然后,基于Spartan6器件平台和ISE软件套件,在ISE下完成了各有限域运算部件和各电路模块的Verilog HDL描述、综合、布局布线和静态时序分析,在iSim下完成了功能仿真和时序仿真,在PlanAhead下完成了位置约束。根据最后的时序报告可知,所设计的RS编码器最高时钟频率为276MHz,所设计的RS解码器最高时钟频率为201MHz。最后,基于上述研究,提出了一种满足JPWL规定码型连续解码的解码器架构,以及一种在不增加资源占用的前提下使可配置RS编解码器设计最为简单的码型方案。
[Abstract]:Reed-Solomon code / RS code is an excellent channel coding method, especially suitable for correcting continuous burst errors, such as DVDCD, digital TV, digital image. Digital audio, deep space detection DVB, digital communication system. JPEG2000 wireless transmission standard has been widely used in engineering fields such as DAB. The main header, block header and other important information of the image data frame are protected by RS code. Therefore, it is very meaningful to study the hardware implementation of RS decoding. Because the most popular algorithm of RS decoding is BM algorithm, this paper firstly introduces the BM algorithm of RS decoding and its various improved versions in detail. Then, the circuit block diagram and hardware complexity of BM algorithm are analyzed. The software simulation of the riBM algorithm with short critical path and regular circuit structure is carried out with C for the RSH255239) code. The correctness of the algorithm is verified. The step decoding algorithm based on the properties of adjoint value matrix and its improved versions are also studied in this paper. The key determinant calculation circuit in the step decoding algorithm is designed. In this paper, various kinds of finite field computing components are designed by using the digital circuit design methods, such as state transition diagram, algorithm dependence graph, and so on. The RS decoder based on the riBM algorithm and the modules that may be used in the RS decoder. The designed RS decoder works in pipeline mode. Codewords can be decoded in a continuous input decoder. Then, based on the Spartan6 device platform and ISE software suite. The Verilog HDL description, synthesis, layout, routing and static timing analysis of each finite field operation unit and each circuit module are completed under ISE. The function simulation and timing simulation are completed under iSim, and the position constraint is completed under PlanAhead. According to the final time sequence report, we can know. The designed RS encoder has a maximum clock frequency of 276 MHz and the designed RS decoder has a maximum clock frequency of 201 MHz. Finally, based on the above research. In this paper, a decoder architecture that meets the requirements of JPWL code type continuous decoding is proposed, and a simple scheme for designing configurable RS codec without increasing resource consumption is proposed.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22;TN791

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