一种12位高精度、低功耗电流舵与R-2R电阻混合型DAC的设计

发布时间：2018-01-05 12:25

本文关键词：一种12位高精度、低功耗电流舵与R-2R电阻混合型DAC的设计　出处：《深圳大学》2015年硕士论文　论文类型：学位论文

【摘要】：信号处理在通信系统、控制系统和计算机系统中起着重要作用,信号处理任务一般由数字信号处理器(DSP)、微控制器(MCU)及微处理器(MPU)实现。然而自然界中的信号是模拟信号,所以数模转换器(DAC)作为连接数字系统与模拟世界的接口变得不可或缺。移动终端的快速发展促进了低功耗数模转换器的需求,因此,研究高精度、低功耗DAC具有重要意义。本文首先分析了三种常见结构的DAC,通过比较各种结构的优缺点,设计了一种12位10 MHz的电流舵与R-2R梯形电阻混合型DAC。设计采用了5+3+4的分段方式,从结构角度有效地降低了DAC的功耗,其中最高五位采用温度计编码电流舵结构,中间三位采用二进制编码电流舵结构,最低四位采用R-2R梯形电阻结构。电流舵中的电流源采用共源共栅结构,有效地提高了输出阻抗;同时在电流源差分开关下面串联一对PMOS管,以降低时钟馈通(Clock Feedthrough)对输出电压的影响。考虑设计的DAC高精度的要求,在版图的设计中,采用层次对称式电流源选通方式来消除梯度误差和对称误差。此外,采用了同步锁存器电路和交叉点降低电路,有效地减小了DAC的输出毛刺。本文中设计的DAC使用TSMC 0.18μm Mixed-Siganl 1P6M CMOS工艺完成了电路的设计和版图实现,并使用Spectre仿真验证DAC的功能和性能。在1.8 V电源电压下,差分输出电压摆幅为±1.0 V,静态功耗为1.3 m A。积分非线性误差小于0.15 LSB,微分非线性误差小于0.04 LSB,当输入正弦信号为300 KHz、采样时钟为10 MHz时的无杂波动态范围(SFDR)约为68 d B。测试结果表明,本文设计的12位DAC的DNL±9.5LSB,INL±13.5LSB。
[Abstract]:Signal processing plays an important role in communication system, control system and computer system. Microcontroller (MCU) and microprocessor (MPU) are implemented. However, signals in nature are analog signals. So DAC) as the interface between digital system and analog world becomes indispensable. The rapid development of mobile terminal promotes the demand of low power DAC. Low power DAC is of great significance. Firstly, this paper analyzes three kinds of common structure DACs, and compares the advantages and disadvantages of each structure. A 12-bit 10 MHz current rudder and R-2R trapezoidal resistance hybrid DAC are designed. The design adopts 534 piecewise mode, which can effectively reduce the power consumption of DAC from the point of view of structure. Among them, the highest five are thermometer coded current rudder structure, the middle three are binary coded current rudder structure, the lowest four are R-2R trapezoidal resistance structure, and the current source in the current rudder is a common source common-grid structure. The output impedance is improved effectively; At the same time, a pair of PMOS transistors are connected in series under the current source differential switch. In order to reduce the impact of clock feed through (clock feed through) on the output voltage. Consider the high accuracy of the DAC design in the layout design. The hierarchical symmetric current source is used to eliminate gradient error and symmetry error. In addition, synchronous latch circuit and crossing point lowering circuit are used. The output burr of DAC is reduced effectively. The DAC designed in this paper uses TSMC 0.18 渭 m Mixed-Siganl 1P6M. CMOS process completes the circuit design and layout implementation. The function and performance of DAC are verified by Spectre simulation. The differential output voltage swing is 卤1.0 V at 1.8V power supply voltage. The static power consumption is 1.3 Ma, the integral nonlinear error is less than 0. 15 LSBs, the differential nonlinear error is less than 0. 04 LSBs, and the input sinusoidal signal is 300 KHz. When the sampling clock is 10 MHz, the dynamic range of clutter free SFDR is about 68 dB. The test results show that the DNL 卤9.5 LSB of the 12-bit DAC is designed in this paper. INL 卤13.5LSB.
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792;TN911.7

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