低噪声斩波Sigma-Delta调制器的设计

发布时间：2018-01-05 12:40

本文关键词：低噪声斩波Sigma-Delta调制器的设计　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：现代社会中数字领域高速发展,作为数字领域与模拟世界的桥梁,模拟数字转换器(ADC)起到了至关重要的作用。没有模拟数字转换器,自然界中时域与幅值连续的信号就无法使用数字领域的信号处理系统进行操作。由于模拟数字转换器的重要性,人们在这个领域做出了很多探索,使得ADC得到了飞速的发展。过采样技术使得模拟数字转换器的精度得到了很大的提升,因此过采样型ADC在工业设计生产过程中得到了广泛的应用。调制器与数字抽取滤波器是Sigma-Delta数模转换器的两大组成部分。其中调制器完成的是模拟信号量化的功能。本文设计了一个过采样型Sigma-Delta调制器,系统级为单环四阶全前馈型结构,该结构能降低对输入信号幅度的要求。主环路由积分器级联组成,全差分运算放大器采用开关电容共模反馈。为了得到更好的线性度,本设计中采用的是一位量化器。时钟电路采用两相非交叠时钟。输入信号带宽为200Hz,为抑制低频噪声第一级积分器采用斩波技术消除低频闪烁噪声。论文前部分将结合过采样调制器原理阐述一些基本结构的选取思路,论文后部分包括MATLAB中系统级设计,电路各模块的设计与仿真,整体电路的设计与仿真以及版图级的设计。本课题系统级设计在SIMULINK平台下进行。电路组成模块搭建成系统级模块进行系统级仿真,确定电路基本性能及参数要求。电路级设计在CADENCE SPECTRE平台下进行,完成各模块的电路级设计,并对各模块性能进行仿真,最终完成整体电路搭建并仿真。版图级设计在CADENCE平台下进行,使用标准0.5μm CMOS N阱工艺对整体电路进行版图设计并完成后仿。本设计在带宽为200Hz的情况下对整体电路进行仿真。输入信号为21.4Hz,幅度为1V时,仿真的结果显示噪声谱密度中噪声基底小于-120d B,信噪比达到103d B,有效位数达16.83位。
[Abstract]:With the rapid development of the digital field in modern society, as the bridge between the digital field and the analog world, the analog-to-digital converter (ADC) plays an important role. There is no analog-to-digital converter. Because of the importance of analog to digital converters, people have made a lot of exploration in this field because of the importance of signal processing systems in the digital domain because of the continuous signal in time domain and amplitude in nature. With the rapid development of ADC, the precision of analog to digital converter has been greatly improved by over-sampling technology. Therefore, oversampling ADC has been widely used in industrial design and production. Modulator and digital decimation filter are two major components of Sigma-Delta digital-to-analog converter, in which modulator is finished. The function of analog signal quantization is obtained. In this paper, an oversampling Sigma-Delta modulator is designed. The system level is a single-loop four-order full-feedforward structure which can reduce the requirement of input signal amplitude. The main loop is composed of integrator cascade. The full differential operational amplifier uses switched capacitor common-mode feedback to obtain better linearity. In this design, a bit quantizer is used. The clock circuit uses a two-phase non-overlapping clock. The input signal bandwidth is 200Hz. In order to suppress the low-frequency noise the chopping technique is used to eliminate the low-frequency scintillation noise in the first stage integrator. The later part of the thesis includes the system-level design of MATLAB, the design and simulation of each module of the circuit. The design and simulation of the whole circuit and the layout level design. The system-level design of the subject is carried out under the SIMULINK platform. The circuit component module is built into the system-level module for system-level simulation. The circuit level design is carried out under the CADENCE SPECTRE platform, the circuit level design of each module is completed, and the performance of each module is simulated. Finally, the whole circuit is built and simulated. The layout level design is carried out under the CADENCE platform. Use of standard 0. 5 渭 m CMOS. The layout of the whole circuit is designed by N-well process and the simulation is completed. The whole circuit is simulated with the bandwidth of 200Hz. The input signal is 21.4Hz. When the amplitude is 1 V, the simulation results show that the noise base is less than -120 dB, the signal-to-noise ratio is 103 dB and the effective bit number is 16.83 bits in the noise spectrum density.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761

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