超外差接收机中频率综合器核心电路设计

发布时间：2018-01-07 23:01

  本文关键词：超外差接收机中频率综合器核心电路设计　出处：《东南大学》2015年硕士论文　论文类型：学位论文

  更多相关文章： 超外差接收机 频率综合器 锁相环 环形压控振荡器 CML分频器 工艺角补偿 NMOS开关电荷泵

【摘要】：随着无线通信和无线控制的发展,无线控制设备已经覆盖到了各个领域。而国内在此方面还未有成熟的芯片,目前已有的芯片大多来自国外大公司和国内逆向设计公司。巨大的市场需求和国内缺乏的技术促使形成了这一产业化项目。频率综合器一般可以分成三类：直接模拟频率综合器、直接数字频率综合器以及锁相环频率综合器。由于锁相环结构易于片上集成,面积小,成本低,从而被目前多数移动通信芯片采用,也成为本文针对超外差结构收发芯片采用的结构。本文的研究内容是超外差接收机中核心电路频率综合器的设计。对其中可用的各类频率综合器结构进行了分析,总结了超外差接收机和各种频率综合器的基本工作原理,包括整数型和小数型。根据实际要求选择了整数型频率综合器,对其进行了模块和环路分析。本文研究的PLL频率综合器核心子模块包括：VCO、分频器、PFD.CP和LPF。详细深入的阐述了其中各核心子模块设计,从选型,辅助结构创新到结构优化给出了完整的设计思路,并完成完整的设计、布图流程,最终通过0.5μn CMOS工艺MPW流片,实现了300-450MHz宽频率锁定范围,3-5.5V宽电源电压范围,-40～125℃宽工作温度范围,在带负载全工艺角条件下提供了四路正交输出信号幅度大于200mV,工作电流小于3mA的频率综合器。本文的创新点在于,四级差分环形振荡器的设计中采用了工艺角检查电路,通过独特的二分工艺角迟滞锁定对应补偿,实现了宽频率、宽电压、宽温度范围的压控特性曲线。在高速CML分频器的设计中,增加了创新的自适应调节输出点电压和尾电流补偿电路。基于基本的电荷泵结构实现全NMOS开关和充电响应速度增强电路。针对产品级芯片设计,增加了辅助的LDO降低功耗和噪声干扰,增加了系统电流镜控制电路来调节测试,增加了过流检查电路来降低芯片的失效风险,并同时实现过流自动恢复功能来保证各种恶劣环境下环路的始终锁定,以及芯片的正常工作。频率综合器的发明是为了产生高精准的倍频或同步时钟,应用于具体的各种接收机、发射机、通信中的调制解调和数字集成电路中的同步时钟产生等。本文涉及的315MHz和433.92MHz超外差结构收发芯片应用在的短距离无线通信和无线控制领域,由于其频段开放,应用前景十分广泛,包括各类无线控制的消费类电子,安防设备,智能家居设备等。
[Abstract]:With the development of wireless communication and wireless control, wireless control devices have been covered in various fields. However, there is no mature chip in this field in China. At present, most of the existing chips come from large foreign companies and domestic reverse design companies. The huge market demand and the lack of technology at home have led to this industrialization project. Frequency synthesizers can be divided into three categories:. Direct analog frequency synthesizer. Direct digital frequency synthesizer and PLL frequency synthesizer. Because the PLL structure is easy to integrate on chip, the area is small and the cost is low, so it is adopted by most mobile communication chips. The research content of this paper is the design of the core circuit frequency synthesizer in the superheterodyne receiver. The structure of all kinds of frequency synthesizer is analyzed. . The basic working principles of the superheterodyne receiver and various frequency synthesizers, including integer type and fractional type, are summarized. The integer frequency synthesizer is selected according to the actual requirements. The core sub-modules of the PLL frequency synthesizer in this paper include: VCO, frequency divider. PFD.CP and LPF. Detailed and in-depth elaboration of each of the core sub-module design, from selection, auxiliary structure innovation to structural optimization give a complete design ideas, and complete the complete design, layout flow. Finally, 300-450 MHz wide frequency locking range and 3-5.5 V wide power supply voltage range are realized by 0.5 渭 n CMOS MPW wafer. At a wide working temperature range of -40 鈩，

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