60V 功率U-MOSFET失效分析与再设计

发布时间：2018-02-27 07:43

本文关键词： 功率MOSFET U-MOSFET 元胞终端　出处：《西南交通大学》2015年硕士论文　论文类型：学位论文

【摘要】：功率MOSFET是功率电子系统中一个关键的元器件,它决定着控制系统的效率与成本。世界上至少50%的电力系统是由功率半导体器件作为控制。其在消费电子、工业电子、医疗电子、航空航天与交通运输业等方面具有重要的影响。碳排放给环境带来的负面影响与日俱增,对功率电子系统的效率与性能提出了更高的要求。沟槽型功率场效应管(U-MOSFET)因其具有芯片面积小、导通电阻低、开关速度快等性能优势而广受市场青睐。U-MOSFET器件的优化设计、准确的失效分析、高可靠性等是学术界与工业界研究的重点。本论文将主要对一款失效的60V U-MOSFET芯片进行失效分析,并完成60VU-MOSFET芯片的高可靠性设计。具体研究内容如下：(1)对失效的60V U-MOSFET芯片的流片测试数据进行数值统计分析,得出芯片导通电阻指标失效,初步定位60V U-MOSFET芯片失效在于芯片版图设计与元胞设计。(2)分析60V U-MOSFET失效芯片版图,结合版图理论,排除由于版图原因导致失效。对元胞TEM图进行分析,建立元胞物理模型,对导通电阻进行物理方程推导,并结合数值仿真验证,得出60V U-MOSFET芯片失效原因来自于栅极沟槽两边的Pbody区在沟槽底部发生穿通,导致外延电阻局部增大,从而引起器件导通电阻失效。(3)在完成60V U-MOSFET芯片失效分析后,对60V U-MOSFET芯片的元胞与终端进行重新优化设计,通过理论与仿真分别得到了导通电阻54353Ω、阈值电压2.947V、耐压81.2V的60V U-MOSFET元胞,和击穿电压68V的终端结构。并通过将芯片硅体内击穿点限制在元胞与终端交界的Pbody区,有效解决电压从元胞向终端过渡引起的振荡。(4)对重新设计的60V U-MOSFET芯片进行版图绘制,并进行流片。通过对裸片与封装测试数据的数值统计分析,最终得到阈值电压2.959V、60V电压下漏电流140.649nA、导通电阻2.77mQ,250/μA电流下击穿电压69.111V、栅极正向漏电流18.509nA、栅极反向漏电流10.305nA的60V U-MOSFET芯片。成功完成60V U-MOSFET芯片从仿真到流片的研发设计。
[Abstract]:Power MOSFET is a key component in power electronic systems, which determines the efficiency and cost of control systems. At least 50% of the world's power systems are controlled by power semiconductor devices. Aerospace and transportation have important impacts. The negative impact of carbon emissions on the environment is increasing. The efficiency and performance of power electronic system are required higher. Because of its advantages of small chip area, low on-resistance and fast switching speed, groove-type power field-effect transistor (PFTs) has been widely used in the market to optimize the design of .U-MOSFET devices. Accurate failure analysis, high reliability and so on are the focus of academic and industrial research. In this paper, a failure analysis of 60V U-MOSFET chip is carried out. And the high reliability design of 60VU-MOSFET chip is completed. The initial location of 60V U-MOSFET chip failure lies in chip layout design and cell design. (2) Analysis of 60V U-MOSFET chip layout. Combined with layout theory, the failure caused by layout is eliminated. The cellular TEM diagram is analyzed and a cellular physical model is established. The physical equation of the on-resistance is deduced, and the results of numerical simulation show that the failure of 60V U-MOSFET is due to the fact that the Pbody region on either side of the gate groove passes through at the bottom of the groove, which results in the local increase of the epitaxial resistance. After the failure analysis of 60V U-MOSFET chip is completed, the cell and terminal of 60V U-MOSFET chip are redesigned and optimized. The on-resistance 54353 惟, threshold voltage 2.947 V and voltage 81.2 V of 60V U-MOSFET cell are obtained by theory and simulation, respectively. And breakdown voltage 68V terminal structure. By limiting the breakdown point in the silicon chip to the Pbody region at the junction between the cell and the terminal, we can effectively solve the oscillation caused by the voltage transition from the cell to the terminal) and plot the layout of the redesigned 60V U-MOSFET chip. Through the numerical statistical analysis of the test data of the bare sheet and the package, Finally, a 60V U-MOSFET chip with a threshold voltage of 2.959V / 60 V and a breakdown voltage of 69.111V at a threshold voltage of 2.959V / 渭 A, a gate forward leakage current of 18.509nA and a gate reverse drain current of 10.305nA, was obtained. The 60V U-MOSFET chip was successfully developed from simulation to chip design.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386.1

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