基于CML的高速串行发送器的研究与设计

发布时间：2018-03-09 01:35

本文选题：高速串行发送　切入点：均衡问题　出处：《电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着科技的进步,信息交流量逐渐增大,高速信号的处理和传输已成为发展趋势。接口电路作为收发数据的关键对数据的传输及处理都有着极为重要的影响。然而,传统的接口电路无法满足高速率条件下信号的处理,这就需要有新的技术、新的规范来支持高速数据的接受和发送。发送器作为接口电路的一部分,将对片内数据进行相应的处理,在达到指标要求之后将数据发出,发出的数据同时要满足接受器对数据的最低要求。随着数据传输率的提高,发送器的设计也将面临更多的问题,对相应指标的要求也会变得更高。本文对高速信号传输、接口原理及相关技术等进行了分析和讨论,在此基础上结合55nm CMOS工艺设计了一款速率为5Gbps的高速串行发送器,并完成了仿真验证与版图设计。文章内容主要包括以下几个方面:1、对高速接口电路的相关理论进行了研究,并对其实现技术及方式进行了分析、比较,从而筛选出本文设计所采用的低压差分串行传输技术和CML(Current Mode Logic)实现方式。2、对高速串行发送器设计中面临的问题进行了研究,主要包括信号完整性问题、均衡问题以及带宽扩展等相关问题。并对这些问题的解决方法进行了讨论。3、基于55nm CMOS工艺并结合高频信号的特点,完成了对发送器模块的设计,其中包括并串转换结构、单端转差分结构、电平位移结构、CML驱动结构。并对每一部分及整体模块进行了仿真验证。4、对数模混合版图设计的相关问题和技术进行了研究,并在此基础上完成了对发送器电路的版图设计。
[Abstract]:With the progress of science and technology, the amount of information exchange is increasing, and the processing and transmission of high-speed signal has become a trend. Interface circuit as the key to receive and send data has an extremely important impact on the transmission and processing of data. However, The traditional interface circuit can not satisfy the signal processing under the condition of high speed, which requires new technology and new specification to support the high-speed data receiving and transmitting. The transmitter is part of the interface circuit. The in-chip data will be processed accordingly, and the data will be sent out after meeting the target requirements. The data sent out must also meet the minimum requirements of the receiver for the data. With the increase of the data transmission rate, The design of the transmitter will also face more problems, and the requirements of the corresponding indicators will become higher. This paper analyzes and discusses the high-speed signal transmission, the principle of interface and related technologies, etc. On this basis, a 5Gbps high-speed serial transmitter is designed in combination with 55nm CMOS process, and the simulation verification and layout design are completed. The main contents of this paper include the following aspects: 1. The related theory of high-speed interface circuit is studied. The realization technology and mode are analyzed and compared, and the low voltage differential serial transmission technology and CML(Current Mode logic mode. 2. The problems in the design of high speed serial transmitter are studied. It mainly includes signal integrity problem, equalization problem and bandwidth expansion problem, and discusses the solution of these problems. Based on 55nm CMOS technology and the characteristics of high frequency signal, the transmitter module is designed. It includes parallel series conversion structure, single end transfer differential structure, level displacement structure and CML driver structure. Finally, the simulation verification of each part and the whole module is carried out, and the related problems and techniques of digital and analog mixed layout design are studied. On this basis, the layout design of the transmitter circuit is completed.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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