基于最大时域瞬态噪声的去耦电容选择方法

发布时间：2018-03-19 17:44

本文选题：集成电路　切入点：最大时域瞬态噪声　出处：《电子与信息学报》2017年11期 　论文类型：期刊论文

【摘要】：针对传统的基于频域目标阻抗的去耦电容选择方法存在过度设计的问题,该文提出基于最大时域瞬态噪声的去耦电容选择方法。首先,利用板级电流可由一系列三角脉冲近似合成这一性质,推导出了去耦电容瞬态电压噪声达到局部最大值的时刻及时域瞬态阻抗应该满足的条件,并通过分析VRM支路最大瞬态电压噪声确定了去耦电容的去耦时间范围;其次,通过研究去耦电容时域瞬态阻抗曲线的性质和特点,制定了去耦电容的选择标准。最后,提出基于最大时域瞬态噪声的去耦设计方案。通过对4个具有典型激励输入的实例进行去耦设计,结果表明,在输入激励条件相同且满足电压噪声要求的前提下,与传统频域目标阻抗法获得的去耦方案相比,该文提出的算法所需电容数量至少能减少24.59%以上。
[Abstract]:Aiming at the problem of over-design of traditional decoupling capacitance selection method based on target impedance in frequency domain, this paper proposes a decoupling capacitance selection method based on maximum transient noise in time domain. By using the property that the plate current can be approximately synthesized by a series of triangular pulses, the condition that the transient impedance in the time domain of decoupling capacitor transient voltage noise reaches the local maximum value is deduced. The decoupling time range of decoupling capacitors is determined by analyzing the maximum transient voltage noise of the VRM branch. Secondly, by studying the properties and characteristics of the transient impedance curves of decoupling capacitors in time domain, the selection criteria of decoupling capacitors are established. A decoupling design scheme based on the maximum transient noise in time domain is proposed. Through the decoupling design of four examples with typical excitation input, the results show that the input excitation condition is the same and the requirement of voltage noise is satisfied. Compared with the decoupling scheme obtained by the traditional frequency-domain target impedance method, the proposed method can reduce the number of capacitors required by the proposed algorithm by more than 24.59% at least.
【作者单位】：西安电子科技大学电路CAD研究所;西安电子科技大学超高速电路设计与电磁兼容教育部重点实验室;
【基金】：国家自然科学基金项目(61501345) 中央高校基本科研业务费(JB150212)~~
【分类号】：TN40

【相似文献】