基于FPGA的高吞吐率CCMP协议的研究与实现

发布时间：2018-04-04 08:23

本文选题：802.11i标准　切入点：CCMP协议　出处：《华中科技大学》2015年硕士论文

【摘要】：随着无线网络的普及应用,其安全性面临巨大的挑战,802.11b标准定义的WEP安全协议无法抵御密钥恢复攻击,因此2004年IEEE无线标准小组公布了802.11i安全补充标准,其关键在于提出了安全高效的CCMP加密协议。随着无线网络速度的提升,基于软件和传统硬件实现协议难以满足系统吞吐率的需求,因此需要采用并行高效的FPGA硬件平台实现CCMP安全协议。本文在深入研究CCMP协议工作机制及其核心加密算法AES的基础上,以高吞吐率为目标,设计了基于FPGA的硬件系统。首先进行架构设计将系统划分为高性能AES模块、AES_CCM模块、格式化模块、主控模块等四个主要部分。然后进行子模块设计,在实现AES模块时采取轮融合技术,进而缩减周期数,提高数据吞吐率;在实现AES_CCM模块时,采用双AES核技术,确保AES_CBC_MAC模块和AES_CTR模块并行执行,提高运算效率;在格式化模块中,设计了数据缓冲结构,使本系统具备更好的兼容性,以便处理不同速率的数据流;在主控模块及子模块的控制流设计过程中,采取优化控制信号等方法,降低关键路径延迟。最后在合理设计架构并提高子模块运算效率的基础上,实现基于FPGA的高吞吐率CCMP协议硬件系统设计。基于Modelsim仿真软件和集成逻辑分析仪对CCMP硬件系统进行仿真验证。然后在Xilinx Vivado开发环境中,以Virtex-7为目标FPGA,进行综合实现以及时序分析,得出系统最高数据吞吐率可达2.185 Gbps。通过与传统设计的全面性能比较,结果表明本文提出的设计方案较为合理,在系统吞吐率、资源利用率等方面均有所提升。
[Abstract]:With the popularization and application of wireless network, the security of WEP protocol defined by 802.11b standard cannot resist the attack of key recovery. So in 2004, the 802.11i security supplement standard was published by the IEEE Wireless Standards Group.The key is to propose a secure and efficient CCMP encryption protocol.With the improvement of wireless network speed, it is difficult to meet the requirements of system throughput based on software and traditional hardware implementation protocols, so it is necessary to use parallel and efficient FPGA hardware platform to implement CCMP security protocol.On the basis of deeply studying the working mechanism of CCMP protocol and its core encryption algorithm AES, this paper designs a hardware system based on FPGA aiming at high throughput.Firstly, the system is divided into four main parts: AESCCM module, format module and main control module.Then the sub-module is designed, the wheel fusion technology is adopted in the realization of AES module, and the cycle number is reduced, and the data throughput is improved. When the AES_CCM module is implemented, the dual AES kernel is adopted to ensure the parallel execution of AES_CBC_MAC module and AES_CTR module.In the format module, the data buffer structure is designed to make the system have better compatibility, in order to deal with the data flow of different rates; in the process of the control flow design of the main control module and sub-module,The critical path delay is reduced by optimizing the control signal.Finally, on the basis of reasonably designing the architecture and improving the operation efficiency of sub-modules, the hardware system design of CCMP protocol with high throughput based on FPGA is realized.Based on Modelsim simulation software and integrated logic analyzer, the CCMP hardware system is simulated and verified.Then in the Xilinx Vivado development environment, taking Virtex-7 as the target, the system is implemented synthetically and the timing is analyzed. It is concluded that the maximum data throughput of the system can reach 2.185 Gbps.Compared with the traditional design, the results show that the design scheme proposed in this paper is reasonable, and the system throughput and resource utilization are improved.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791;TN915.04

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